AT89C51CC03C-RDRIM Atmel, AT89C51CC03C-RDRIM Datasheet - Page 131
![IC 8051 MCU FLASH 64K 64VQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT89C51CC03C-RDRIM
Manufacturer Part Number
AT89C51CC03C-RDRIM
Description
IC 8051 MCU FLASH 64K 64VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-RDRIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03CRDRTR
Available stocks
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Manufacturer
Quantity
Price
- AT89C51CC03C-S3RIM PDF datasheet
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OverRun Condition
Interrupts
4182E–CAN–05/04
Figure 61. Mode Fault Conditions in Slave Mode
Note:
This error mean that the speed is not adapted for the running application:
An OverRun condition occurs when a byte has been received whereas the previous one
has not been read by the application yet.
The last byte (which generate the overrun error) does not overwrite the unread data so
that it can still be read. Therefore, an overrun error always indicates the loss of data.
Three SPI status flags can generate a CPU interrupt requests:
Table 91. SPI Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer
has been completed. SPIF bit generates transmitter CPU interrupt request only when
SPTEIE is disabled.
Mode Fault flag, MODF: This bit is set to indicate that the level on the SS is inconsistent
with the mode of the SPI (in both master and slave modes).
Serial Peripheral Transmit Register empty flag, SPTE: This bit is set when the transmit
buffer is empty (other data can be loaded is SPDAT). SPTE bit generates transmitter
CPU interrupt request only when SPTEIE is enabled.
Flag
SPIF (SPI data transfer)
MODF (Mode Fault)
SPTE (Transmit register empty)
Note: While using SPTE interruption for “burst mode” transfers (SPTEIE=’1’), the
user software application should take care to clear SPTEIE, during the last but one
data reception (to be able to generate an interrupt on SPIF flag at the end of the last
data reception).
when SS is discarded (SS disabled) it is not possible to detect a MODF error in slave
mode because the SPI is internally selected. Also the SS pin becomes a general pur-
pose I/O.
SCK cycle #
SCK
(from master)
MOSI
(from master)
MISO
(from slave)
SS
(slave)
1
z
0
1
z
0
1
z
0
1
z
0
0
MODF detected
MSB
Request
SPI Transmitter Interrupt Request
SPI mode-fault Interrupt Request
SPI transmit register empty Interrupt Request
0
MSB
MSB
1
MODF detected
B6
B6
2
AT89C51CC03
B5
3
B4
4
131
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