MPC565MVR56 Freescale Semiconductor, MPC565MVR56 Datasheet - Page 3

• Manufacturer Part Number: MPC565MVR56
• Description: IC MCU 1M FLASH 56MHZ 388-BGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC565MVR56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 40x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 36 KB
• Interface Type: QSPI/SCI/UART
• Maximum Clock Frequency: 56 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 3
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPC566EVBE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (40-ch x 10-bit)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.2
The MPC565 key features are explained in the following sections.
1.2.1
1.2.2
1.2.3
1.2.4
MOTOROLA
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Fully static design
Four major power saving modes
— On, doze, sleep, deep-sleep and power-down
High-performance core
— PowerPC single issue integer core
— Precise exception model
— Floating point
— Code compression (MPC566 only)
MPC500 system interface (USIU, BBC, L2U)
Periodic interrupt timer, bus monitor, clocks, decrementer and time base
Clock synthesizer, power management, reset controller
External bus tolerates 5-V inputs, provides 2.6-V outputs
Enhanced interrupt controller supports a separate interrupt vector for up to eight external and 40
internal interrupts
IEEE 1149.1 JTAG test access port
Bus supports multiple master designs
USIU supports dual-mapping of Flash to move part of internal Flash memory to external bus for
development
External bus, supporting non-wraparound burst for instruction fetches, with up to 8 instructions
per memory cycle
Exception vector table relocation features allow exception table to be relocated to following
locations:
— 0x0000 0000 - 0x0000 1FFF (normal MPC500 exception table location)
— 0x0001 0000 - 0x0001 1FFF (0 + 64 Kbytes; second page of internal Flash)
— Second internal Flash module
— Internal SRAM
— 0x0FFF_0100 (external memory space; normal MPC500 exception table location)
Detailed Feature List
High Performance CPU System
RISC MCU Central Processing Unit (RCPU)
– Compression reduces usage of internal or external Flash memory
– Compression optimized for automotive (non-cached) applications
– New compression scheme decreases code size to 40% –50% of source
MPC500 System Interface (USIU)
Burst Buffer Controller (BBC) Module
Freescale Semiconductor, Inc.
For More Information On This Product,
MPC565/MPC566 Product Brief
Go to: www.freescale.com
Detailed Feature List
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