HD64F7045F28V Renesas Electronics America, HD64F7045F28V Datasheet - Page 101

• Manufacturer Part Number: HD64F7045F28V
• Description: IC SH2 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7040r

Specifications of HD64F7045F28V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 28.7MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 98
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6. When there are three or fewer instructions in the loop, PC relative instructions (MOVA
7. If there are four or more instructions in the loop, PC relative instructions (MOVA (disp,PC),
8. The SH-DSP does not have a repeat valid flag; repeats become invalid when the RC counter
9. If there are four or more instructions in the loop, the branched instructions including the
10. While the repeat is being executed, interruption is restricted. Figure 4.23 shows the flow for
(disp,PC), R0, or the like) can only be used at the first instruction (instr1).
R0, or the like) cannot be used in the final two instructions.
becomes 0. When the RC counter is not 0 and the PC counter matches the RE register contents,
repeating begins. When the RC counter is set to 0, the repeat program (loop) is invalid but the
loop is executed only once and does not return to the starting instruction of the loop as when
RC is 1. When the RC counter is set to 1, the repeat module is executed only once. Though it
does not return to the repeat program (loop) start instruction, the RC counter becomes zero
when the repeat module is executed.
subroutine call back and return instructions cannot be used for the “inst3” through “inst5”
instructions as branch destination address. If they are executed, the repeat control does not
work correctly. If the branch destination is “RptStart” or any address ahead of it, content of RC
in the SR register is not updated.
each stage of EX. The initial EX stage of interruption or the bus error exception is usually
started immediately after the EX stage of the instruction is completed (indicated by “A”).
However, in the EX stage of the next instr0, only the bus error exception can be designated by
“B” to continue. At the EX stage of instr1, neither interruption nor bus exception can be
continued by “C”. Only the EX stage of instr2 can be continued.
Rev. 5.00 Jun 30, 2004 page 85 of 512
Section 4 Instruction Features
REJ09B0171-0500O