M30853FWGP#U5 Renesas Electronics America, M30853FWGP#U5 Datasheet - Page 297
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122256/m30853fwgp_u5_sml.jpg)
M30853FWGP#U5
Manufacturer Part Number
M30853FWGP#U5
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FWGP#U5
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
320KB (320K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FWGP#U5M30853FWGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30853FWGP#U5M30853FWGP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
3
. v
J
2
0
Figure 22.1 Intelligent I/O Block Diagram
C
intelligent I/O communication.
ISCLK0
ISRxD0
1
NOTES:
9
0 .
8 /
Figures 22.1 shows a block diagram of the intelligent I/O. Figure 22.2 shows a block diagram of the
B
1. Each register is placed in a reset state after the G1BCR0 register
f
Two-phase
pulse signal
is applied
1
0
3
5
f
f
f
supplies the clock.
0
1
8
2n
3
G
J
7
u
o r
Overflow of bit 15 in the base timer
Overflow of bit 9 in the base timer
0 -
. l
u
INPC1
INPC1
INPC1
0
1
/ ISCLK1
/ ISRxD1
BCK1 and BCK0
INPC1
INPC1
INPC1
INPC1
INPC1
p
, 1
0
11
10
3
(
2
0
1
2
M
Communication
3
4
5
6
7
0
3
0
5
2
C
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Digital
Filter
Filter
Filter
Filter
Filter
Filter
Filter
Filter
8 /
Page 272
, 5
Unit 0
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
10 : f
11 : f
M
1
1
1
1
1
1
1
1
BT1
BT1
BT1
BT1
BT1
BT1
BT1
BT1
BTS
3
Request from the INT pin
2
00
00
00
00
00
00
00
00
C
f o
8 /
0
1
DIV4 to DIV0
CTS1 and CTS0
CTS1 and CTS0
CTS1 and CTS0
CTS1 and CTS0
CTS1 and CTS0
CTS1 and CTS0
CTS1 and CTS0
CTS1 and CTS0
BTRE
4
Select
Select
Select
Select
Select
Select
Select
Select
5
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Divider
2(n+1)
9
) T
4
Function
Function
Gate
Gate
1
1
GT
GT
0
0
Request by matching the base timer with the G1PO0 register
ISTxD0
Prescaler
DIV4 to DIV0 bits, BCK1 and BCK0 bits : Bits in the G1BCR0 Register
BTS : Bit in the G1BCR1 Register
CTS1 and CTS0, DF1 and DF0, GT, PR : Bits in the G1TMCRj Register (j = 0 to 7)
MOD2 to MOD0 : Bits in the G1POCRj Register
BTRE : Bit in the G1POCR0 Register
Function
Prescaler
Function
Base timer reset
in the communication unit 1
f
BT1
1
1
PR
PR
0
0
Communication
G1TM0, G1PO0
Register
G1TM1, G1PO1
Register
G1TM2, G1PO2
Register
G1TM3, G1PO3
Register
G1TM4, G1PO4
Register
G1TM5, G1PO5
Register
G1TM6, G1PO6
Register
Base Timer
Unit 1
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Output
Output
Output
Output
PWM
PWM
PWM
PWM
000 to 010
000 to 010
111
Ch0 to Ch7
interrupt request signal
OUTC1
OUTC1
OUTC1
OUTC1
MOD2 to MOD0
MOD2 to MOD0
22. Intelligent I/O
111
4
5
6
7
OUTC1
OUTC1
OUTC1
/BE1
OUTC1
OUT
1
/ISCLK1
3
0
2
/ISTxD1
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