DF2338VFC25V Renesas Electronics America, DF2338VFC25V Datasheet - Page 331
![IC H8S/2300 MCU FLASH 144QFP](/photos/12/22/122201/df2338vfc25v_sml.jpg)
DF2338VFC25V
Manufacturer Part Number
DF2338VFC25V
Description
IC H8S/2300 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2338VFC25V.pdf
(1246 pages)
Specifications of DF2338VFC25V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
106
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2338VFC25V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 331 of 341
- Download datasheet (2Mb)
3.5
This is a state in which the bus has been released in response to a bus request from a bus master
other than the CPU. While the bus is released, the CPU halts except for internal operations.
Bus masters other than the CPU may include the direct memory access controller (DMAC) and
data transfer controller (DTC).
For further details, refer to the relevant microcontroller hardware manual.
3.6
The power-down state includes both modes in which the CPU stops operating and modes in which
the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode,
software standby mode, and hardware standby mode. There are also two other power-down
modes: medium-speed mode and module stop mode. In medium-speed mode the CPU and other
bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation
of individual modules, other than the CPU. For details, refer to the relevant microcontroller
hardware manual.
3.6.1
A transition to sleep mode is made if the SLEEP instruction is executed while the software
standby bit (SSBY) in the system control register (SYSCR) is cleared to 0. In sleep mode, CPU
operations stop immediately after execution of the SLEEP instruction. The contents of CPU
registers are retained.
3.6.2
A transition to software standby mode is made if the SLEEP instruction is executed while the
SSBY bit in SYSCR is set to 1. In software standby mode, the CPU and clock halt and all on-chip
operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is
supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain
in their existing states.
Bus-Released State
Power-Down State
Sleep Mode
Software Standby Mode
Rev. 4.00 Feb 24, 2006 page 315 of 322
Section 3 Processing States
REJ09B0139-0400
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