MC9S12DJ256
Target Applications
> Automotive applications
> Industrial control
Overview
Freescale Semiconductor’s HCS12 family of
microcontrollers (MCUs) is the next generation
of the highly successful 68HC12 architecture.
Using Freescale’s industry-leading 0.25 µs Flash,
the MC9S12DJ256 is part of a pin-compatible
family that scales from 32 KB to 512 KB of
Flash memory. The DJ256 provides an upward
migration path from Freescale’s 68HC08,
68HC11 and 68HC12 architectures for
applications that need larger memory, more
peripherals and higher performance. Also, with
the increasing number of CAN/J1850-based
electronic control units (ECUs), its multiple
network modules support this environment by
enabling highly efficient communications
between different network buses.
16-bit Microcontrollers
3 x SPI
16-Key Wake-Up
Vreg 5V to 2.5V
J1850 Interface
IRQ Ports
5 x CAN
2.0 A/B
2 x SCI
BDLC
I
2
C
HCS12 CPU
8-ch., 10-bit
12 KB RAM
ATD0
Enhanced Capture Timer
8-ch., 8-bit/4-ch., 16-bit
256 KB Flash
8-ch., 16-bit
PWM
4 KB EEPROM
8-ch., 10-bit
ATD1
Features
High-Performance 16-bit HCS12 CPU Core
> 25 MHz bus operation at 5V for 40 ns
On-Chip Debug Interface
> Dedicated serial debug interface
> On-chip breakpoints
Network Modules
> Two msCAN modules implementing the CAN
> One J1850 module
Integrated Third-Generation Flash Memory
> In-application reprogrammable
> Self-timed, fast programming
> 5V Flash program/erase/read
> Flash granularity—512 byte Flash erase/
> Four independently programmable Flash arrays
> Flexible block protection and security
4 KB Integrated EEPROM
> Flexible protection scheme for protection
> EEPROM can be programmed in 46 µs
10-bit Analog-to-Digital Converter (ADC)
> Two, 8-channel ADCs
> 7 µs, 10-bit single conversion time, scan
minimum instruction cycle time
2.0 A/B protocol
• Five receive buffers per module with FIFO
• Three transmit buffers per module with
• Fast Flash page erase—20 ms (512 bytes)
• Can program 16 bits in 20 µs while
2 byte Flash program
against accidental program or erase
mode available
storage scheme
in burst mode
internal prioritization
> Opcode compatible with the 68HC11
> C-optimized architecture produces extremely
> Real-time in-circuit emulation and debug
> Read/write memory and registers while
> Ability to link modules for higher buffer count
> Programmable bit rate up to 1 Mbps
> FIFO receive approach superior for
> Ability to send and receive messages across
> Flexibility to change code in the field
> Efficient end-of-line programming
> Total program time for 256 KB code
> Reduces production programming cost
> No external high voltage or charge
> Virtual EEPROM implementation, Flash array
> Can erase one array while executing code
> Can erase 4 bytes at a time and program
> Fast, easy conversion from analog inputs like
> Can effectively have 3.5 µs conversion
Benefits
and 68HC12
compact code
without expensive and cumbersome
box emulators
running at full speed
event-driven networks
an SAE J1850 serial communication network
is less than 10 seconds
through ultra-fast programming
pump required
usable for EE extension
from another
2 bytes at a time for calibration, security,
personality and diagnostic information
temperature, pressure and fluid levels to digital
values for CPU processing
time by sampling same signal with
both ADCs