C8051F122-GQ Silicon Laboratories Inc, C8051F122-GQ Datasheet - Page 173

• Manufacturer Part Number: C8051F122-GQ
• Description: IC 8051 MCU FLASH 128K 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F122-GQ

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x10b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 12 bit, 2 Channel
• No. Of I/o's: 64
• Ram Memory Size: 8448Byte
• Cpu Speed: 100MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1226

Bits 7 – 0: Byte 3 (bits 31 – 24) of MAC0 Accumulator.
Bits 7 – 0: Byte 2 (bits 23 – 16) of MAC0 Accumulator.
Bits 7 – 0: Byte 1 (bits 15 – 8) of MAC0 Accumulator.
*Note:
*Note:
*Note:
Bit7
Bit7
Bit7
R
R
R
The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 12.7. MAC0ACC3: MAC0 Accumulator Byte 3
SFR Definition 12.8. MAC0ACC2: MAC0 Accumulator Byte 2
SFR Definition 12.9. MAC0ACC1: MAC0 Accumulator Byte 1
Bit6
Bit6
Bit6
R
R
R
Bit5
Bit5
Bit5
R
R
R
Bit4
Bit4
Bit4
R
R
R
Rev. 1.4
Bit3
Bit3
Bit3
R
R
R
C8051F120/1/2/3/4/5/6/7
Bit2
Bit2
Bit2
R
R
R
C8051F130/1/2/3
Bit1
Bit1
Bit1
R
R
R
SFR Address: 0x95
SFR Address: 0x96
SFR Address: 0x94
SFR Page: 3
SFR Page: 3
SFR Page: 3
Bit0
Bit0
Bit0
R
R
R
00000000
00000000
Reset Value
00000000
Reset Value
Reset Value
173