MCF5249LAG120 Freescale Semiconductor, MCF5249LAG120 Datasheet - Page 340

IC MPU 32BIT COLDF 144-LQFP

MCF5249LAG120

Manufacturer Part Number
MCF5249LAG120
Description
IC MPU 32BIT COLDF 144-LQFP
Manufacturer
Freescale Semiconductor
Series
MCF524xr

Specifications of MCF5249LAG120

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
120MHz
Connectivity
I²C, IDE, MMC, SPI, UART/USART
Peripherals
DMA, I²S, POR, Serial Audio, WDT
Number Of I /o
34
Program Memory Type
ROMless
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 4x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
144-LQFP
Family Name
MCF5xxx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
120MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.8V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
LQFP
Maximum Clock Frequency
120 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Program Memory Size
8KB
Cpu Speed
120MHz
Embedded Interface Type
I2C, QSPI, UART
Digital Ic Case Style
LQFP
No. Of Pins
144
Rohs Compliant
Yes
For Use With
M5249C3 - KIT EVAL FOR M5249 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5249LAG120
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5249LAG120
Manufacturer:
FREESCALE
Quantity:
20 000
Freescale Semiconductor, Inc.
BTST.B #0,(A7)+
BNE.B END
MOVE.B TXCNT,D0;Get value from the transmitting counter
BEQ.S END;If no more data, branch to end
MOVE.B DATABUF,-(A7);Transmit next byte of data
MOVE.B (A7)+,MBDR
MOVE.B TXCNT,D0;Decrease the TXCNT
SUBQ.L #1,D0
MOVE.B D0,TXCNT
BRA.S EMASTX;Exit
END LEA.L MBCR,-(A7);Generate a STOP condition
BCLR.B #5,(A7)+
EMASTX RTE; Return from interrupt
MASR MOVE.B RXCNT,D0;Decrease RXCNT
SUBQ.L #1,D0
MOVE.B D0,RXCNT
BEQ.S ENMASR;Last byte to be read
MOVE.B RXCNT,D1;Check second-to-last byte to be read
EXTB.L D1
SUBI.L #1,D1;
BNE.S NXMAR; Not last one or second last
LAMAR BSET.B #3,MBCR;Disable ACK
BRA NXMAR
ENMASR BCLR.B #5,MBCR; Last one, generate 'STOP'signal
NXMAR MOVE.B MBDR,RXBUF; Read data and store RTE
Generation of Repeated START
At the end of data transfer, if the master still wants to communicate on the bus, it can generate another START signal followed
by another slave address without first generating a STOP signal. A program example follows.
RESTART MOVE.B MBCR,-(A7); Another START (RESTART)
BSET.B #2, (A7)
MOVE.B (A7)+, MBCR
MOVE.B CALLING,-(A7);Transmit the calling address, D0=R/W-
MOVE.B CALLING,-(A7);
MOVE.B (A7)+, MBDR
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