C8051F124-GQ Silicon Laboratories Inc, C8051F124-GQ Datasheet - Page 270

• Manufacturer Part Number: C8051F124-GQ
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F124-GQ

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 100-TQFP, 100-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 8-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F12x
• Maximum Speed: 50 MHz
• No. Of I/o's: 64
• Ram Memory Size: 8448Byte
• Cpu Speed: 50MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1228

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
270
Mode
Status
Code
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
START condition transmitted.
Repeated START condition transmitted.
Slave Address + W transmitted. ACK
received.
Slave Address + W transmitted. NACK
received.
Data byte transmitted. ACK received.
Data byte transmitted. NACK received.
Arbitration Lost.
Slave Address + R transmitted. ACK received.
Slave Address + R transmitted. NACK
received.
Data byte received. ACK transmitted.
Data byte received. NACK transmitted.
Table 19.1. SMB0STA Status Codes and States
SMBus State
Rev. 1.4
Load SMB0DAT with Slave Address +
R/W. Clear STA.
Load SMB0DAT with Slave Address +
R/W. Clear STA.
Load SMB0DAT with data to be transmit-
ted.
Acknowledge poll to retry. Set STO +
STA.
1) Load SMB0DAT with next byte, OR
2) Set STO, OR
3) Clear STO then set STA for repeated
START.
1) Retry transfer OR
2) Set STO.
Save current data.
If only receiving one byte, clear AA (send
NACK after received byte). Wait for
received data.
Acknowledge poll to retry. Set STO +
STA.
Read SMB0DAT. Wait for next byte. If
next byte is last byte, clear AA.
Set STO.
Typical Action