C8051F061-GQ Silicon Laboratories Inc, C8051F061-GQ Datasheet - Page 243
![IC 8051 MCU 64K FLASH 64TQFP](/photos/12/20/122063/c8051f061-gq_sml.jpg)
C8051F061-GQ
Manufacturer Part Number
C8051F061-GQ
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F061-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN/I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
24
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F060DK
Minimum Operating Temperature
- 40 C
On-chip Adc
2-ch x 16-bit
On-chip Dac
2-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1215
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25 ms (and TOE set), a Timer 4 overflow indicates a SCL low timeout; the Timer 4 interrupt service routine
can then be used to reset SMBus0 communication in the event of an SCL low timeout.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
BUSY
Bit7
R
BUSY: Busy Status Flag.
0: SMBus0 is free.
1: SMBus0 is busy.
ENSMB: SMBus Enable.
This bit enables/disables the SMBus serial interface.
0: SMBus0 disabled.
1: SMBus0 enabled.
STA: SMBus Start Flag.
0: No START condition is transmitted.
1: When operating as a master, a START condition is transmitted if the bus is free. (If the
bus is not free, the START is transmitted after a STOP is received.) If STA is set after one or
more bytes have been transmitted or received and before a STOP is received, a repeated
START condition is transmitted.
STO: SMBus Stop Flag.
0: No STOP condition is transmitted.
1: Setting STO to logic 1 causes a STOP condition to be transmitted. When a STOP condi-
tion is received, hardware clears STO to logic 0. If both STA and STO are set, a STOP con-
dition is transmitted followed by a START condition. In slave mode, setting the STO flag
causes SMBus to behave as if a STOP condition was received.
SI: SMBus Serial Interrupt Flag.
This bit is set by hardware when one of 27 possible SMBus0 states is entered. (Status code
0xF8 does not cause SI to be set.) When the SI interrupt is enabled, setting this bit causes
the CPU to vector to the SMBus interrupt service routine. This bit is not automatically
cleared by hardware and must be cleared by software.
AA: SMBus Assert Acknowledge Flag.
This bit defines the type of acknowledge returned during the acknowledge cycle on the SCL
line.
0: A "not acknowledge" (high level on SDA) is returned during the acknowledge cycle.
1: An "acknowledge" (low level on SDA) is returned during the acknowledge cycle.
FTE: SMBus Free Timer Enable Bit.
0: No timeout when SCL is high.
1: Timeout when SCL high time exceeds limit specified by the SMB0CR value.
TOE: SMBus Timeout Enable Bit.
0: No timeout when SCL is low.
1: Timeout when SCL low time exceeds limit specified by Timer 4, if enabled.
ENSMB
R/W
Bit6
Figure 20.8. SMB0CN: SMBus0 Control Register
STA
R/W
Bit5
STO
R/W
Bit4
Rev. 1.2
R/W
Bit3
SI
C8051F060/1/2/3/4/5/6/7
R/W
Bit2
AA
FTE
R/W
Bit1
SFR Address:
SFR Page:
TOE
R/W
Bit0
0xC0
0
Addressable
Reset Value
00000000
Bit
243
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