TMPA910CRAXBG Toshiba, TMPA910CRAXBG Datasheet
TMPA910CRAXBG
Specifications of TMPA910CRAXBG
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TMPA910CRAXBG Summary of contents
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... TOSHIBA 32-Bit RISC Microcontroller TX09 Series TMPA910CRAXBG TENTATIVE Semiconductor Company ...
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... Caution about the Electrostatic Discharge (ESD) Sensitivity of This Product This product is an electrostatic discharge sensitive (ESDS) product that requires extra caution in handling. For ESD test data of this product, please contact your local Toshiba sales representative. *************************************************************************************************************** ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries ...
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Introduction - Notes on the registers - This device has SFR (Special Function Register) each IP (Peripheral circuits). SFR is shown as following in this data book lists ・ IP lists show the register name, address and ...
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... Overview and Features TMPA910CRA is a 32-bit RISC microprocessor with a built-in ARM9 TMPA910CRAXBG is a 361-pin BGA package product. Features of the product are as follows: (1) ARM926EJ-S manufactured by ARM is used. • Data cache: 16 Kbytes • Instruction cache: 16 Kbytes (2) Maximum operating frequency: 200 MHz (3) A 7-layer multi bus system is used. ...
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UART: 2 channels • Channel 0: supports Full UART / supports IrDA1.0 mode. • Channel 1: supports only 3 pins: TXD, RXD, and CTS. (10) USB controller: 1 channel • Supports USB (REV2.0). • Supports high communication speed (480Mbps) ...
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I/O port: 114 pins (22) DMA controller: 8 channels (23) NAND-flash memory interface: 2 channels • Easy connection to NAND-flash memory. • Supports both 2LC (2 values) and 4LC (4 values) types. • Supports 8-bit data bus and 512/2048-byte ...
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Data Cache 16Kbyte CPU Inst. LCD LCDC Controller (Bus Master3) LCD Data Process LCDDA Accelerator (Bus Master4) CPU Data Interrupt Controller I/F (2ch) NANDF Controller (2ch) SD Host Controller CPU Data (2ch) Synchronous Serial Port (2ch) CMOS ...
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Pin Configuration and Functions This section provides a TMPA910CRA pin configuration diagram, names of I/O pins, and brief description of their functions. 2.1 Pin configuration diagram (Top View) Figure 2.1.1 shows the TMPA910CRA pin configuration ...
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Ball Pin name No. C3 SP0/TCK D4 SP1/TMS K8 DVSSCOM1 D3 SP2/TDI B1 DVCC3IO1 E5 SP5/TDO E4 SP4/RTCK F5 SP3/TRSTn G6 DVCC3CMS1 G5 PF6/I2C1CL F4 PF7/I2C1DA/INTC H7 PF1/CMSHSY J7 PE7/CMSD7 E3 PF2/CMSHBK D2 PF3/CMSVSY K8 DVSSCOM2 F3 PF0/CMSPCK L7 PE6/CMSD6 ...
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Ball Pin name No. W14 PL4/I2SSCLK T12 DVCC3I2S1 U13 PL1/I2S0CLK/SP1CLK P11 PM3/I2S1MCLK W16 PM1/I2S1CLK N11 PL3/I2S0MCLK/SP1DI L10 DVSSCOM15 R12 PL0/I2S0WS/SP1FSS U14 DVCC3I2S2 T13 PR0/RESETOUTn W15 PR1/SMCWPn/FCOUT W17 DVCC1A6 U15 DVCCM1 R13 SC3/D19 V16 SA0/D0 P12 SC6/D22 M11 DVSSCOM16 P13 SC5/D21 ...
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Ball Pin name No. A15 SL1/DMCDCLKN A14 DVSSCOM35 B14 SK1/DMCSDQM1/DMCDDM1 D11 SJ7/SMCAVDn F10 DVCCM14 G12 SJ1/DMCWEn A13 SL3/SMCCLK F11 DVCC1A11 B11 DVSSCOM36 E11 SJ0/SMCOEn B12 SJ3/DMCCASn A12 DVSSCOM37 B10 SH5/SMCCS2n E10 SH6/SMCCS3n A12 DVSSCOM38 D10 SH3/SMCCS0n A11 SJ6/DMCCKE F10 DVCCM15 ...
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Pin Names and Functions The names and functions of I/O pins are shown below. Pins associated with memory are switched to either of two types of MPMC (MPMC0/1) depending on the status of the external pin “SELMEMC”. Table 2.2.1 ...
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Table 2.2.1 Pin names and functions (2/8) Pin name Number of Input/Output pins − SJ3 DMCCASn 1 Output DMCCASn Output − SJ4 DMCBA0 1 Output DMCBA0 Output − SJ5 DMCBA1 1 Output DMCBA1 Output − SJ6 DMCCKE 1 Output DMCCKE ...
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Pin name Number of pins Input/Output − SM0 1 X1 Input − SM1 1 X2 Output SM2 - 1 XT1 Input − SM3 1 XT2 Output − SM4 1 RESETn Input − SM5 1 TEST0n Input − SM6 to SM7 ...
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Table 2.2.1 Pin names and functions (4/8) Pin name Number of pins Input/Output − SU0 1 LCLCP Output − SU1 1 LCLAC Output − SU2 1 LCLLE Output − SU3 1 LCLFP Output − SU4 1 LCLLP Output − SU5 ...
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Table 2.2.1 Pin names and functions (5/8) Pin name Number of pins Input/Output PA0 to PA7 Input 8 KI0 to KI7 Input PB0 to PB7 Output 8 KO0 to KO7 Output PC0 to PC1 Output 2 KO8 to KO9 Output ...
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Table 2.2.1 Pin names and functions (6/8) Pin name Number of pins Input/Output PF2 Input 1 CMSHBK Input PF3 Input 1 CMSVSY Input PF6 Input/Output 1 I2C1CL Input/Output PF7 Input/Output I2C1DA Input/Output 1 INTC Input PG0 to PG3 Input/Output 4 ...
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Table 2.2.1 Pin names and functions (7/8) Pin name Number of pins Input/Output PM0 Input/Output 1 I2S1WS Input/Output PM1 Input/Output 1 I2S1CLK Input/Output PM2 Input/Output 1 I2S1DATO Output PM3 Input/Output 1 I2S1MCLK Output PN0 Input/Output U0TXD 1 Output SIR0OUT Output ...
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Table 2.2.1 Pin names and functions (8/8) Pin name Number of pins Input/Output PT4 Input/Output 1 U1TXD Output PT5 Input/Output 1 U1RXD Input PT6 Input/Output 1 U1CTSn Input PT7 Input/Output 1 X1USB Input DVCC1Ax 14 Power supply DVCC1B 2 Power ...
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Pin Functions and Initial Values Arranged by Type of Power Supply - 1 (DVCCM ) Power supply Typical pin to be used name SA0 to SA7 SB0 to SB7 SC0 to SC7 SD0 to SD7 SE0 to SE7 SF0 to ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 2 (DVCCM) Power supply to Typical pin name be used SL0 SL1 DMCDCLKN SL2 SL3 DVCCM SL4 DMCDDQS0 SL5 DMCDDQS1 SL6 SL7 PR0 RESETOUTn PR1 PR2 Note 1: ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 3 (DVCC3IO) Power supply Typical pin name to be used SM2 SM3 SM4 SM5 SM6 SM7 SN0 SN1 SELDVCCM SN2 SP0 SP1 SP2 DVCC3IO SP3 SP4 SP5 SV0 ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 4 (DVCC3IO) Power supply Alternative Typical pin name to be used PC0 PC1 PC2 PC3 MLDALM PC4 PC5 MLDALMn PC6 PC7 PG0 SDC0DAT0 PG1 SDC0DAT1 PG2 SDC0DAT2 PG3 ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 5 (DVCC3LCD) Power supply Typical pin name to be used ST0 to ST7 SU0 SU1 SU2 SU3 DVCC3LCD SU4 SU5 SU6 SU7 PJ0 to PJ7 LD8 to LD15 ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 7 (DVCC3I2S) Power supply Typical pin name to be used PL0 PL1 PL2 PL3 DVCC3I2S PL4 PM0 PM1 PM2 PM3 Note 1: Pin names "SA0 through SA7, …, ...
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Pin Functions and Initial Values Arranged by Type of Power Supply – 9 (USB) Power supply Typical pin name to be used SR0 SR1 AVDD3C/T SR3 SR4 Note 1: Pin names "SA0 through SA7, …, and SW0 through SW6" are ...
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Operational Description This chapter provides a brief description of the CPU circuitry of the TMPA910CRA. 3.1 CPU This section describes the basic operations of the CPU of the TMPA910CRA for each block. Note that this document provides only an ...
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Reset Operation Before resetting the TMPA910CRA, make sure that the power supply voltage is within the operating range, oscillation from the internal oscillator is stable at 20 system clock cycles (0.8 μ MHz) at least, ...
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Exceptions The TMPA910CRA includes 7 types of exception, and each of them has privileged processing mode. Exception Reset Undefined instruction execution Software interrupt (SWI) instruction Pre-fetch abort Data abort IRQ FIQ TENTATIVE Address 0x00000000 0x00000004 0x00000008 It is used ...
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Multilayer AHB The TMP910CRA uses a multilayer AHB bus system with 7 layers. Data Cache 16 KB LCD Controller (Bus Master 3) LCD Data Process Accelerator (Bus Master 4) Interrupt Controller I/F (2 ch) NANDF Controller ...
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... JTAG Interface 3.2.1 Overview The TMPA910CRAXBG provides a boundary-scan interface that is compatible with Joint Test Action Group (JTAG) specifications and uses the industry-standard JTAG protocol (IEEE Standard 1149.1•1990 <Includes IEEE Standard 1449.1a•1993>). This chapter describes the JTAG interface, with the descriptions of boundary scan and the pins and signals used by the interface ...
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... Set this pin to 0 except for Boundary Scan Mode. The TMPA910CRA operates as regular Debug Mode. 0 Note: Debugging is not available if the internal BOOT is carried out with AM1 = 1 and AM0 = 1. The TMPA910CRA operates in Boundary Scan Mode 1 TENTATIVE Note TMPA910CRAXBG TDI TDO TMS TCK TRSTn RTCK Operation mode ...
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... Outline of Boundary Scan With the evolution of ever-denser integrated circuits (ICs), surface-mounted devices, double-sided component mounting on printed-circuit boards (PCBs), and set-in recesses, in-circuit tests that depend upon physical contact like the connection of the internal board and chip has become more and more difficult to use. The more ICs have become complex, the lager and more difficult the test program became ...
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JTAG Controller and Registers The processor contains the following JTAG controller and registers: Instruction register Boundary scan register Bypass register Device identification register Test Access Port (TAP) controller JTAG basically operates to monitor the TMS input signal with the ...
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The bypass register is 1 bit wide. When the TAP controller is in the Shift-DR (bypass) state, the data on the TDI pin is shifted into the bypass register, and the bypass register output shifts to the date out on ...
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Boundary Scan Register The boundary scan register provides all the inputs and outputs of the TMPA910CRA processor except some analog outputs and control signals. The pins of the TMPA910CRA allow any pattern to be driven by scanning the data ...
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TAP Controller The processor incorporates the 16-state TAP controller stipulated in the IEEE JTAG specification. 3.2.9 Resetting the TAP Controller The TAP controller state machine can be put into the Reset state by the following method. Assertion of the ...
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TENTATIVE The following paragraphs describe each of the controller states. The left column in Figure 3.2.6 is the data column, and the right column is the instruction column. The data column and instruction column reference the data register (DR) and ...
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TENTATIVE • Shift-DR In this controller state, the test data register connected between TDI and TDO shifts data out serially. When the TAP controller is in this state, then it remains in the Shift-DR state if TMS is held low, ...
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TENTATIVE • Exit 1-IR This is a temporary controller state. When the TAP controller is in this state, it moves to either the Pause-IR state if TMS is held low, or the Update-IR state if TMS is held high. • ...
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Boundary Scan Order Table 3.2.2 shows the boundary scan order with respect to the processor signals. TDI -> 1(PF6) -> 2(PF7) … -> 230(SU4) -> 231(PK7) -> TDO Table 3.2.2 JTAG Scan Order of the TMPA910CRA Processor Pins Pin ...
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Instructions Supported by the JTAG Controller Cells This section describes the instructions supported by the JTAG controller cells of the TMPA910CRA. (1) EXTEST instruction The EXTEST instruction is used for external interconnect tests. The EXTEST instruction permits BSR cells ...
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SAMPLE/PRELOAD instruction This instruction targets the boundary scan register between TDI and TDO. As its name implies, the SAMPLE/PRELOAD instruction provides two functions. SAMPLE allows the input and output pads monitored. While it does ...
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BYPASS instruction This instruction targets the bypass register between JTDI and JTDO. The bypass register provides the shortest serial path that bypasses the IC (between JTDI and JTDO) when the test does not require control or monitoring of the ...
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Memory Map The memory map of the TMPA910CRA is as follows: Table 3.3.1 Outline of Access to Internal Areas Characteristics CPU Address Width CPU Data Bus Width Internal Operation Frequency Minimum Bus Cycle Internal RAM Internal Boot ROM Internal ...
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Internal Start Address BOOT ROM Mode 0x0000_0000 Internal ROM 0x0000_2000 0x0000_4000 SMCCS0n 0x0100_0000 Reserved area 0x2000_0000 Reserved area 0x2100_0000 SMCCS0n 0x4000_0000 DMCCSn 0x6000_0000 SMCCS1n 0x8000_0000 Reserved area 0xA000_0000 SMCCS2n 0xC000_0000 Reserved area 0xE000_0000 SMCCS3n 0xF000_0000 ...
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Start Internal Address BOOT ROM Mode 0x0000_0000 Internal ROM 0x0000_2000 0x0000_4000 SMCCS0n 0x0100_0000 Reserved area 0x2000_0000 Reserved area 0x2100_0000 SMCCS0n 0x4000_0000 DMCCSn 0x6000_0000 SMCCS1n 0x8000_0000 Reserved area 0xA000_0000 SMCCS2n 0xC000_0000 Reserved area 0xE000_0000 SMCCS3n 0xF000_0000 ...
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... MB 0xF431_0000 0xF431_0FFF 0xF440_0000 0xF440_0FFF Note1: Any area without the addresses shown above is a reserved area. Do not access any reserved area. Note2: TMPA910CRAXBG does not support UART1 DMAC transfer. Figure 3.3.3 Memory Map (Details of Internal Registers) TENTATIVE Details of Internal IO SysCtrl WDT ...
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Boot mode The TMPA910CRA has boot modes determined by the external pin setting. 1. Boot memory setting Mode Setting Pin RESETn AM1 AM0 Start from the external 16-bit NOR Flash memory 0 1 (Internal BOOT ROM cannot be seen) ...
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System Controller 3.4.1 Remapping Function The remapping function allows the 8 Kbyte area of the built-in RAM in the TMPA910CRA to be accessed from the two memory areas (0x0000_0000 to 0x0000_1FFF and 0xF800_2000 to 0xF800_3FFF). Write access to the ...
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BOOT Mode 0x0000_0000 Built-in ROM 16 KB 0x0000_2000 0x0000_4000 External area SMCCS0n 0x0100_0000 Reserved area 0x2000_0000 Reserved area 0x2100_0000 External area 0xF000_0000 Built-in IO area 0xF800_0000 Built-in RAM-3: 0xF800_2000 8 KB (Remap) Built-in RAM-0: 0xF800_4000 16 KB Built-in RAM-1: 0xF800_8000 ...
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Register Descriptions The following lists the SFRs: Register Address Name (base+) Remap 0x0004 1. Remap Register Bit Bit Symbol − [31:1] [0] REMAP [Description] a. <REMAP> the register that enables the REMAP function. By writing arbitrary data, ...
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Clock Controller 3.5.1 Overview The clock controller is a circuit that controls all clocks in the MCU. It has the following features using a clock multiplication circuit (PLL), the clock controller supplies a clock ...
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Block Diagram < > ...
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The clock restrictions are defined below. Select an appropriate clock for the intended applications within the restrictions. Table 3.5.1 Clock Restrictions (a) f OSCH (High speed oscillator frequency) (b) f PLL (PLL output frequency) (c) f FCLK (Frequency for the ...
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Operational Descriptions 3.5.3.1 Register Descriptions The following lists the SFRs: Register Address Name (base+) SYSCR0 0x000 System Control Register 0 SYSCR1 0x004 System Control Register 1 SYSCR2 0x008 System Control Register 2 SYSCR3 0x00C System Control Register 3 SYSCR4 ...
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SYSCR0 (System Control Register 0) Bit Bit Type Symbol − − [31:8] [7:6] USBCLKSEL R/W [5] Reserved R/W − − [4] [3] Reserved R/W − − [2] [1] Reserved R/W − − [0] [Description] a. <USBCLKSEL> Selects the USB ...
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SYSCR1 (System Control Register 1) Bit Bit Type Symbol − − [31:3] [2:0] GEAR R/W [Description] a. <GEAR> Programs the clock gear. 0y000: fc 0y001: fc/2 0y010: fc/4 0y011: fc/8 0y1xx: Reserved TENTATIVE Reset Value Undefined Read as undefined. ...
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SYSCR2 (System Control Register-2) Bit Bit Type Symbol − − [31:8] [7] Reserved R/W − − [6:2] [1] FCSEL R/W [0] LUPFLAG RO [Description] a. <FCSEL> Selects the clock to be output from the PLL. 0y0: f OSCH 0y1: ...
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SYSCR3 (System Control Register 3) Bit Bit Type Symbol − − [31:8] [7] PLLON R/W − − [6] [5] C2S R/W [4:0] ND R/W [Description] a. <PLLON> Controls the operation of the PLL. 0y0: OFF 0y1 <C2S> ...
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SYSCR4 (System Control Register 4) Bit Bit Type Symbol − − [31:8] [7:4] RS R/W [3:2] IS R/W [1:0] FS R/W [Description] a. <RS> PLL constant value setting 3 Program the following values according to PLL multiplying factor and ...
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SYSCR5 (System Control Register 5) Bit Bit Type Symbol − − [31:1] [0] PROTECT RO [Description] By setting a dual key to the SYSCR6 and SYSCR7 registers, protection (write operation to certain SFRs in the clock controller) can be ...
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SYSCR6 (System Control Register 6) Bit Bit Type Symbol − − [31:8] [7:0] P-CODE0 WO [Description] a. <P-CODE0> Used to set the protect code 0. 8. SYSCR7 (System Control Register 7) Bit Bit Type Symbol − − [31:8] [7:0] ...
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CLKCR5 (Clock Control Register-5) Bit Bit Type Symbol − − [31:7] [6] Reserved R/W − − [5:4] [3] R/W SEL_SMC_ MCLK [2] R/W SEL_TIM45 [1] R/W SEL_TIM23 [0] SEL_TIM01 R/W [Description] a. <SEL_SMC_MCLK> Selects SMC_MCLK. 0y1: f HCLK 0y0: ...
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System Clock Controller The system clock controller generates a clock to be supplied to the CPU core (f other built-in I/Os (f HCLK SYSCR1<GEAR2:0> to change the high speed clock gear 8-speed (fc, fc/2, ...
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PLL output: f PLL Lock-up timer <LUPFLAG> CPU clock f FCLK PLL operation and lock-up start Setting example – 2: PLL stop (SYSCR2) LUP: Dummy instruction execution (Note) (SYSCR3) <FCSEL> <PLLON> PLL output: f PLL CPU clock f ...
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Boot ROM TMPA910CRA contains a boot ROM for loading a user program to the internal RAM. The following loading methods are supported. 3.6.1 Operation Modes TMPA910CRA has two operation modes: external memory mode and internal boot ROM mode. Either ...
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Hardware Specifications of the Internal Boot ROM (1) Memory map Figure 3.6.1 shows a memory map of BOOT mode. The internal boot ROM consists ROM and is assigned to addresses from 0x0000_0000 to 0x0000_3FFF. Internal boot ...
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The boot ROM elimination function After the boot sequence is executed in BOOT mode, remapping is executed and the internal boot ROM area changes into RAM. BOOT mode 0x0000_0000 Internal ROM 16 KB 0x0000_2000 0x0000_4000 Unused area 0x2100_0000 External ...
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Outline of Boot Operation USB can be selected as the transfer source of boot operation. After reset, operation of the boot program on the internal boot ROM follows the flow chart shown in Figure 3.6.3. In any case, the ...
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Vector in ROM 0x0000 0000 BOOT ROM (16KB) ・ ・ Vector in RAM 0xF800 2000 User program LOAD area: vector area included (8KB) 0xF800 4000 User program LOAD area (40KB) 0xF800 E000 Boot program work space and stack space area ...
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Example of USB Boot In boot from USB, user program vector is downloaded to 8KB of Remap area (0xF800_2000 to 0xF800_3FFF), program is downloaded to 40KB of internal RAM area (0xF800_4000 to 0xF800_DFFF). Boot program remaps the area, and ...
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CPU status and port settings ARM926EJ-S starts in supervisor mode after reset, and the boot program executes all programs in supervisor mode without any mode changes. No port settings are required as ports used in the boot program are ...
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Download via USB (1) Connection example Figure 3.6.5 shows an example of USB connection (assuming that NOR Flash is program memory) PC Figure 3.6.5 USB connection example (2) Overview of the USB interface specifications Set the oscillation frequency for ...
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The following shows an overview of the USB communication flow. Host (PC) Send GET_DESCRIPTOR. Connection recognition Send DESCRIPTOR information. Data transfer Send a microcontroller information command. Convert Motorola S3 format data. Send microcontroller information data. Check data Send the user ...
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TENTATIVE The following shows the connection of Vendor class request. The table below shows the setup command data structure. Table 3.6.6 Setup Command Data Structure Field bmRequestType 0x40 bRequest 0x00, 0x02, 0x04 wValue 0x00~0xFFFF wIndex 0x00~0xFFFF wLength 0x0000 The table ...
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The table below shows standard request commands. Table 3.6.8 Standard request commands Standard request GET_STATUS CLEAR_FEATURE SET_FEATURE SET_ADDRESS GET_DESCRIPTOR SET_DESCRIPTOR GET_CONFIGRATION SET_CONFIGRATION GET_INTERFACE SET_INTERFACE SYNCH_FRAME The table below shows information to be returned by GET_DESCRIPTOR. Table 3.6.9 Replies to GET_DISCRIPTOR ...
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Configuration Descriptor Field bLength 0x09 bDescriptorType 0x02 wTotalLength 0x0020 bNumInterfaces 0x01 bConfigurationValue 0x01 iConfiguration 0x00 bmAttributes 0x80 MaxPower 0x31 Interface Descriptor Field bLength 0x09 bDescriptorType 0x04 bInterfaceNumber 0x00 bAlternateSetting 0x00 bNumEndpoints 0x02 bInterfaceClass 0xFF bInterfaceSubClass 0x00 bInterfaceProtocol 0x50 iIinterface 0x00 ...
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Endpoint Descriptor (When the USB host supports USB2.0) Field <Endpoint1> blength 0x07 bDescriptorType 0x05 bEndpointAddress 0x81 bmAttributes 0x02 wMaxPacketSize 0x0200 bInterval 0x00 <Endpoint2> bLength 0x07 bDescriptor 0x05 bEndpointAddress 0x02 bmAttributes 0x02 wMaxPacketSize 0x0200 bInterval 0x00 Endpoint Descriptor (When the USB ...
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The table below shows information replied to the microcontroller information command. Table 3.6.10 Information Replied to the Microcontroller Information Command Microcontroller information TMPA910CR 0x54,0x4D,0x50,0x41,0x39,0x31,0x30,0x43,0x52,0x20,0x20,0x20,0x20,0x20,0x20 Note: produnct name in the Microcontroller information includes 6 spaces at the end of the product ...
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Description of the USB boot program operation The boot program transfers data in Motorola S3 format sent from the PC to the internal RAM. The user program starts operating after data transfer is completed. The start address of the ...
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Usage Note Following are the note when use the BOOT ROM. 1．Using TIMER0 Timer0 is used in the BOOT sequence. (Then Timer0control<TIM0EN> Timer0 operation is enable status possible that an interrupt of Timer0 may be ...
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Interrupts 3.7.1 Functional Overview The interrupts of the TMPA910CRA has the following features: • Supports 28 interrupt sources. • Assigns 32 levels of fixed hardware(H/W) priorities to the interrupt sources (to be used if multiple interrupt requests of the ...
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Logic circuit of Interrupt request VICIntEnable [31:0] VICINTSOURCE [31:0] VICSoftInt [31:0] TENTATIVE VICIntSelect [31:0] Figure 3.7.2 Status flag relation TMPA910CRA- 83 TMPA910CRA VICIRQStatus [31:0] VICFIQStatus [31:0] VICRawInterrupt [31:0] 2009-12-10 ...
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Operational Description For Interrupt Control(VIC), FIQ (Fast Interrupt Request) and IRQ (Interrupt Request) are available. The TMPA910CRA only has one FIQ source. FIQ is a low- latency interrupt and has the highest priority level. In handling FIQ, Interrupt Service ...
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Interrupt vector flowchart An interrupt occurs (IRQ) CPU branches to 0x00000018, and jumps to the Interrupt Service Routine Read the VICADDRESS register so that other higher priority interruptions than current interruption can be re-enabled If necessary, “PUSH” the register ...
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Interrupt Sources Interrupt source number (Note) 0 WDT 1 RTC 2 Timer01 3 Timer23 4 Timer45 5 GPIOD:INTA (TSI), INTB ch0 ch1 8 ADC 9 Reserved 10 UART ch0 11 UART ...
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SFRs The following lists the SFRs: Register Address Name (base+) VICIRQSTATUS 0x0000 VICFIQSTATUS 0x0004 VICRAWINTR 0x0008 VICINTSELECT 0x000C VICINTENABLE 0x0010 VICINTENCLEAR 0x0014 VICSOFTINT 0x0018 VICSOFTINTCLEAR 0x001C VICPROTECTION 0x0020 VICSWPRIORITYMASK 0x0024 − 0x0028 VICVECTADDR0 0x0100 VICVECTADDR1 0x0104 VICVECTADDR2 0x0108 VICVECTADDR3 ...
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Register Address Name (base+) VICVECTPRIORITY4 0x0210 VICVECTPRIORITY5 0x0214 VICVECTPRIORITY6 0x0218 VICVECTPRIORITY7 0x021C VICVECTPRIORITY8 0x0220 − 0x0224 VICVECTPRIORITY10 0x0228 VICVECTPRIORITY11 0x022C VICVECTPRIORITY12 0x0230 VICVECTPRIORITY13 0x0234 VICVECTPRIORITY14 0x0238 VICVECTPRIORITY15 0x023C VICVECTPRIORITY16 0x0240 VICVECTPRIORITY17 0x0244 VICVECTPRIORITY18 0x0248 − 0x024C VICVECTPRIORITY20 0x0250 VICVECTPRIORITY21 0x0254 ...
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VICIRQSTATUS (IRQ Status Register) Bit Bit Symbol [31:0] IRQStatus [Description] a. <IRQStatus> This bit shows IRQ interrupt status after masked. Refer the Figure 3.7.2 Status flag relation . IRQStatus [31:0] correspond to interrupt numbers respectively. About ...
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VICRAWINTR (Raw Interrupt Status Register) Bit Bit Symbol [31:0] RawInterrupt [Description] a. <RawInterrupt> This bit shows IRQ interrupt status before masked. Refer the Figure 3.7.2 Status flag relation . RawInterrupt [31:0] correspond to interrupt source numbers ...
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VICINTENABLE (Interrupt Enable Register) Bit Bit Symbol [31:0] IntEnable Bit Bit Symbol [31:0] IntEnable [Description] a. <IntEnable> READ: Status read register of Interrupt Enable/Disable WRITE: Setting register of Interrupt Enable This register can be set only from disable to ...
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VICINTENCLEAR (Interrupt Enable Clear Register) Bit Bit Symbol [31:0] IntEnable Clear [Description] a. <IntEnable Clear> This bit controls interrupt disable. Enable setting of VICINTENABLE register can be cleared, and interruption is disabled. IntEnable Clear [31:0] corresponds to interrupt source ...
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VICSOFTINTCLEAR (Software Interrupt Clear Register) Bit Bit Symbol [31:0] SoftIntClear [Description] a. <SoftIntClear> This bit controls “disable” for software interruption. Software interruption of VICSOFTINT register can be disabled. SoftIntClear [31:0] correspond to interrupt source numbers respectively. ...
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VICSWPRIORITYMASK (Software Priority Mask Register) Bit Bit Symbol − [31:16] [15:0] SWPriorityMask [Description] a. <SWPriorityMask> This register can be set the software priority level. SWPriorityMask [15:0] correspond to priority levels respectively. Example: When SWPriorityMask [15:0] = ...
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VICVECTPRIORITY0 (Vector Priority 0 Register) Bit Bit Symbol − [31:4] [3:0] VectPriority [Description] a. <VectPriority> This register can be set the software priority level of 0y0000 is highest level, and can set 16 level (0y0000 to 0y1111). If multiple ...
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DMAC (DMA Controller) 3.8.1 Functional Overview The DMA controller has the following features: Item Number of channels 8 ch DMA start Hardware request Software request 32 bits × 2 (AHB) Bus master Priority DMA channel 0 (high) to DMA ...
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DMA Transfer Types DMA Transfer DMA Request Direction Generator Memory-to-Peripheral Peripheral 1 Peripheral-to-Memory Peripheral 2 Memory-to-Memory DMAC (Note 2) 3 Peripheral-to-Peripheral Source peripheral 4 Destination peripheral Note 1: Peripheral that can use the single request: UART and LCDDA. Note ...
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Memory-to-Memory Memory 4. Peripheral-to-peripheral 1) Integral multiple of the burst size DMACBREQ Source Peripheral DMACCLR AMBA Bus 2) Single transfer Source DMACSREQ Peripheral DMACCLR AMBA Bus 3) Not Integral Multiple of the burst size DMACBREQ Source DMACSREQ Peripheral DMACCLR ...
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Block Diagram − [15] LCDDA [14] Reserved [13] Reserved [12] I2S1 [11] I2S0 [10] CPU Data. SD buf read [9] SD buf write [8] Reserved [7] Reserved [6] CameraIF0 [5] NANDC0 [4] burst request Reserved [3] Reserved [2] UART0 ...
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Register descriptions The following lists the SFRs.: Address Register Name (base+) DMACIntStaus 0x0000 DMACIntTCStatus 0x0004 DMACIntTCClear 0x0008 DMACIntErrorStatus 0x000C DMACIntErrClr 0x0010 DMACRawIntTCStatus 0x0014 DMACRawIntErrorStatus 0x018 DMACEnbldChns 0x01C DMACSoftBReq 0x020 DMACSoftSReq 0x024 − 0x028 − 0x02C DMACConfiguration 0x030 − 0x034 ...
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Address Register Name (base+) DMACC6SrcAddr 0x1C0 DMACC6DestAddr 0x1C4 DMACC6LLI 0x1C8 DMACC6Control 0x1CC DMACC6Configuration 0x1D0 DMACC7SrcAddr 0x1E0 DMACC7DestAddr 0x1E4 DMACC7LLI 0x1E8 DMACC7Control 0x1EC DMACC7Configuration 0x1F0 − 0xFE0 − 0xFE4 − 0xFE8 − 0xFEC − 0xFF0 − 0xFF4 − 0xFF8 − 0xFFC ...
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DMACIntStatus (DMAC Interrupt Status Register) Bit Bit Symbol − [31:8] [7] IntStatus7 [6] IntStatus6 [5] IntStatus5 [4] IntStatus4 [3] IntStatus3 [2] IntStatus2 [1] IntStatus1 [0] IntStatus0 [Description] a. <IntStatus[7:0]> Indicates the status of the DMAC interrupt after reflecting the ...
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DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register) Bit Bit Symbol − [31:8] [7] IntStatusTC7 [6] IntStatusTC6 [5] IntStatusTC5 [4] IntStatusTC4 [3] IntStatusTC3 [2] IntStatusTC2 [1] IntStatusTC1 [0] IntStatusTC0 [Description] a. <IntTStatusTC[7:0]> Indicates the enabled state of the terminal count ...
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DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register) Bit Bit Symbol − [31:8] [7] IntTCClear7 [6] IntTCClear6 [5] IntTCClear5 [4] IntTCClear4 [3] IntTCClear3 [2] IntTCClear2 [1] IntTCClear1 [0] IntTCClear0 [Description] a. <IntTCClearCH[7:0]> Writing 1 to each bit of this register ...
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DMACIntErrorStatus (DMAC Interrupt Error Status Register) Bit Bit Symbol − [31:8] [7] IntErrStatus7 [6] IntErrStatus6 [5] IntErrStatus5 [4] IntErrStatus4 [3] IntErrStatus3 [2] IntErrStatus2 [1] IntErrStatus1 [0] IntErrStatus0 [Description] a. <IntErrStatus[7:0]> These bits shows status of Raw Error interrupt. i ...
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DMACIntErrClr (DMAC Interrupt Error Clear Register) Bit Bit Symbol − [31:8] [7] IntErrClr7 [6] IntErrClr6 [5] IntErrClr5 [4] IntErrClr4 [3] IntErrClr3 [2] IntErrClr2 [1] IntErrClr1 [0] IntErrClr0 [Description] a. <IntErrClr[7:0]> 0y1: Clear Error interrupt request. TENTATIVE Reset Type Value ...
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DMACRawIntTCStatus (DMAC Raw Interrupt Terminal Count Status Register) Bit Bit Symbol − [31:8] [7] RawIntTCS7 [6] RawIntTCS6 [5] RawIntTCS5 [4] RawIntTCS4 [3] RawIntTCS3 [2] RawIntTCS2 [1] RawIntTCS1 [0] RawIntTCS0 [Description] a. <RawIntTCS[7:0]> Indicates the Raw state of the terminal ...
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DMACRawIntErrorStatus (DMAC Raw Error Interrupt Status Register) Bit Bit Symbol − [31:8] [7] RawIntErrS7 [6] RawIntErrS6 [5] RawIntErrS5 [4] RawIntErrS4 [3] RawIntErrS3 [2] RawIntErrS2 [1] RawIntErrS1 [0] RawIntErrS0 [Description] a. <RawIntErrS[7:0]> Indicates the Raw state of the Error interrupt. ...
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DMACEnbldChns (DMAC Enabled Channel Register) Bit Bit Symbol − [31:8] [7] EnabledCH7 [6] EnabledCH6 [5] EnabledCH5 [4] EnabledCH4 [3] EnabledCH3 [2] EnabledCH2 [1] EnabledCH1 [0] EnabledCH0 [Description] a. <EnabledCH[7:0]> 0y0: Applicable channel bit is cleared when DMA transfer has ...
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DMACSoftBReq (DMAC Software Burst Request Register) Bit Bit Symbol − [31:15] [14] SoftBReq14 − [13:12] [11] SoftBReq11 [10] SoftBReq10 [9] SoftBReq9 [8] SoftBReq8 [7] Reserved [6] Reserved [5] SoftBReq5 [4] SoftBReq4 − [3:2] [1] SoftBReq1 [0] SoftBReq0 [Description] a. ...
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DMACSoftSReq (DMAC Software Single Request Register ) Bit Bit Symbol − [31:16] − [15] [14] SoftSReq14 − [13:12] − [11:4] − [3:2] [1] SoftSReq1 [0] SoftSReq0 [Description] a. <SoftSReq[14:0]> This register is used to configure the DMA single transfer ...
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DMACConfiguration (DMAC Configuration Register) Bit Bit Symbol − [31:3] [2] M2 [1] M1 [0] E [Description] a. <E> Write/read operation can be executed to any of the DMAC registers only when the DMA circuit is active. To perform DMA ...
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DMACC0SrcAddr (DMAC Channel0 Source Address Register) Bit Bit Symbol [31:0] SrcAddr [Description] a. <SrcAddr> Software configures each register directly before the channel is enabled. When the DMAchannel is enabled, the register is updated as the destination address is incremented ...
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DMACC0DestAddr (DMAC Channel0 Destination Address Register) Bit Bit Symbol [31:0] DestAddr [Description] a. <DestAddr> When transfer is taking place, don’t update this register. If you want to change the channel configuration, you must disable the channel first with the ...
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DMACC0LLI (DMAC Channel0 Linked List Item Register) Bit Bit Symbol [31:2] LLI − [1] [0] LM [Description] a. <LLI> The value set to <LLI> must be within 0xFFFF_FFF0. If the LLI is 0, then the current LLI is the ...
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DMACC0Control (DMAC Channel0 Control Register) Bit Bit Symbol [31] I [30] Prot[3] [29] Prot[2] [28] Prot[1] [27] DI [26] SI [25] D [24] S [23:21] Dwidth[2:0] [20:18] Swidth[2:0] [17:15] DBSize[2:0] [14:12] SBSize[2:0] [11:0] TransferSize TENTATIVE Reset Type Value Terminal ...
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The description below applies to all channels. a. <Swidth[2:0]> The transfer source bit width must be an integral multiple of the transfer destination bit width. b. <DBSize[2:0]> Note: The burst size set in DBsize is unrelated to HBURST of ...
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DMACC0Configuration (DMAC Channel0 Configuration Register) Bit Bit Symbol − [31:19] [18] Halt [17] Active [16] Lock [15] ITC [14] IE [13:11] FlowCntrl − [10] [9:6] DestPeripheral − [5] [4:1] SrcPeripheral [0] E Note: Please refer to Table 3.8.2 DMA ...
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This is a DMA request peripheral number in binary. This setting will be ignored if memory is specified as the transfer destination. c. <SrcPeripheral> This is a DMA request peripheral number in binary. This setting will be ignored ...
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Special Function 1) Scatter/gather function When a part of image data is cut off and transferred, the image data is not be handled as consecutive data. The addresses of the image data to be transferred are scattered according to ...
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Linked list operation To use the scatter/gather function, a series of linked lists should be created to define source and destination data areas. LLI enables to transfer unordered multiple blocks sequentially. Each LLI transfers data based on the configuration ...
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Example: When transferring data in the area enclosed by the square 0x00200 0x0A000 0x0B000 0x0C000 DMACCxSrcAddr: 0x0A200 DMACCxDestAddr: Destination address 1 DMACCxLLI: 0x200000 DMACCxControl: Set the number of burst transfers, etc. Linked List 0x0B200(SrcAddr) 0x200000 Dest Addr2 +4 0x200010 +8 ...
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Port Functions The list of the port pin functions and input-output port programming show how to configure each pin. Information on power sources is also provided as different power sources are used for individual external pins. Table 3.9.1 TMPA910CRA ...
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TENTATIVE Table 3.9.2 TMPA910CRA pin assignment (dual-purpose pins) TMPA910CRA- 124 TMPA910CRA 2009-12-10 ...
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TENTATIVE Table 3.9.3 TMPA910CRA address and initial value table TMPA910CRA- 125 TMPA910CRA 2009-12-10 ...
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Data Registers [Notes on data registers] All data registers allow all the 8 bits to be read or written simultaneously also possible to mask certain bits in reading from or writing to the data registers. Data registers ...
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Port Function Settings This section describes the settings of Port A through Port T that can also function as general-purpose ports. Each port should basically be accessed in word (32-bit) units. 3.9.2.1 Port A Port A can be used ...
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GPIOADATA (Port Data Regsiter) Bit Bit Symbol − − [31:8] [7:0] PA[7:0] RO [Description] a. <PA[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOAIS (Port A Interrupt Select Register (Level and ...
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GPIOAIBE (Port A Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol − [31:8] [7:0] PA7IBE to A0IBE [Description] a. <PA7IBE to PA0IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge 4. ...
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GPIOARIS (Port A Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7:0] PA7RIS to PA0RIS [Description] a. <PA7RIS to PA0RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. 0y0: Not ...
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Port B Port B can be used not only as general-purpose output pins but also as key output pins. By enabling open-drain output, Port B is used as key output (KO7-KO0). General-Purpose Output Setting Function Data Value GPIOBDATA General-purpose ...
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GPIOBDATA (Port B Data Register) Bit Bit Symbol − − [31:8] [7:0] PB[7:0] R/W [Description] a. <PB[7:0]> Data register: Stores data. See notes on data registers for bit masking. TENTATIVE Reset Bit Type mask Value − Undefined 0xFF Bm7:0 ...
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GPIOBODE (Port B Open-drain Output Enable Register) Bit Bit Symbol − [31:8] [7:0] PB7ODE to PB0ODE [Description] a. <PB7ODE to PB0ODE> Open-drain output enable register: Selects Push-Pull output or open-drain output. 0y0: Push-Pull output 0y1: Open-drain (Pch disabled) output ...
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Port C The upper 3 bits (bits [7:5]) of Port C can be used as general-purpose input/output pins and the lower 5 bits (bits [4:0]) can be used as general-purpose output pins. Port C can also be used as ...
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MLDALM and PWE settings Input/Output Function Data Value MLDALM GPIOCDATA GPIOCDIR PWE * Bit 7 Bit 6 Bit 5 − − MLDALMn PWM output setting Input/Output Function Data Value GPIOCDATA GPIOCDIR PWM * Bit 7 Bit 6 Bit 5 − ...
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... Even if the power of some internal circuits is cut off, the statuses of external IO can be held. Care should be taken when controlling ports. Furthermore, please pay special attention to the PC2 port control due to its particular circuit configuration. The below chart shows an internal circuit connection diagram. TMPA910CRAXBG GPIOCFR1 GPIOCFR2 (Not used) Initial value/ ...
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Register Address Name (base+) GPIOCDATA 0x03FC GPIOCDIR 0x0400 GPIOCFR1 0x0424 GPIOCFR2 0x0428 GPIOCIS 0x0804 GPIOCIBE 0x0808 GPIOCIEV 0x080C GPIOCIE 0x0810 GPIOCRIS 0x0814 GPIOCMIS 0x0818 GPIOCIC 0x081C GPIOCODE 0x0C00 1. GPIOCDATA (Port C Data Register) Bit Bit Symbol − − [31:8] ...
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GPIOCFR1 (Port C Function Register 1) Bit Bit Symbol − [31:8] [7:2] PC7F1 to PC2F1 [1:0] Reserved [Description] a. <PC7F1 to PC2F1> Function register 1: Controls the function setting. 4. GPIOCFR2 (Port C Function Register 2) Bit Bit Symbol ...
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GPIOCIS (Port C Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] [7] PC7IS − [6] [5] PC5IS − [4:0] [Description] a. <PC7IS, PC5IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIOCIBE ...
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GPIOCIEV (Port C Interrupt Select Register (“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] [7] PC7IEV − [6] [5] PC5IEV − [4:0] [Description] a. <PC7IEV, PC5IEV> Interrupt event register: Select falling edge or rising edge ...
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GPIOCRIS (Port C Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7] PC7RIS − [6] [5] PC5RIS − [4:0] [Description] a. <PC7RIS, PC5RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable ...
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Following table is an example configurations of interrupt register. The configurations of each register and bit are shown below. Table 3.9.5 An example configurations of interrupt register (GPOnIS, GPIOnIBE, GPIOnIEV, GPIOnIE, GPIOnRIS, GPIOnMIS ...
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GPIOCIC (Port C Interrupt Clear Register) Bit Bit Symbol − [31:8] [7] PC7IC − [6] [5] PC5IC − [4:0] [Description] a. <PC7IC, PC5IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared 12. GPIOCODE (Port C Open-drain ...
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Port D Port D can be used as general-purpose input Port D can also be used as interrupt (INTB, INTA), ADC (AN5-AN0), and touch screen control (PX, PY, MX, MY) pins. General-purpose input and Interrupt settings Function Data Value ...
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Register Address Name (base+) GPIODDATA 0x03FC − 0x0400 GPIODFR1 0x0424 GPIODFR2 0x0428 GPIODIS 0x0804 GPIODIBE 0x0808 GPIODIEV 0x080C GPIODIE 0x0810 GPIODRIS 0x0814 GPIODMIS 0x0818 GPIODIC 0x081C − 0x0C00 1. GPIODDATA (Port D Data Register) Bit Bit Symbol − − [31:8] ...
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GPIODFR1 (Port D Function Register 1) Bit Bit Symbol − [31:8] [7:6] Reserved [5:0] PD5F1 to PD0F1 [Description] a. <PD5F1 to PD0F1> Function register 1: Controls the function setting. 3. GPIODFR2 (Port D Function Register 2) Bit Bit Symbol ...
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GPIODIS (Port D Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] [7:6] PD7IS to PD6IS [5:0] Reserved [Description] a. <PD7IS to PD6IS> Interrupt sensitivity register: Selects the interrupt trigger mode from edge-sensitive and level-sensitive. 0y0: Edge-sensitive ...
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GPIODIEV (Port D Interrupt Select Register (“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] [7:6] PD7IEV to PD6IEV [5:0] Reserved [Description] a. <PD7IEV to PD6IEV> Interrupt event register: Selects falling edge or rising edge for ...
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GPIODRIS (Port D Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7:6] PD7RIS to PD6RIS − [5:0] [Description] a. <PD7RIS to PD6RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. ...
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GPIODIC (Port D Interrupt Clear Register) Bit Bit Symbol − [31:8] [7:6] PD7IC to PD6IC − [5:0] [Description] a. <PD7IC to PD6IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Request cleared TENTATIVE Reset Type Value − Undefined ...
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Port E Port E can be used as general-purpose input. Port E can also be used as data input pins for the CMOS image sensor (CMSD7-CMSD0). General-purpose input setting Function Data Value GPIOEDATA General-purpose input * Bit 7 Bit ...
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GPIOEDATA (Port E Data Register) Bit Bit Symbol − − [31:8] [7:0] PE[7:0] RO [Description] a. <PE[7:0]> Data register: Stores data. See notes on data registers for bit masking. 2. GPIOEFR1 (Port E Function Register 1) Bit Bit Symbol ...
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Port F The upper 2 bits (bits [7:6]) of Port F can be used as general-purpose input/output pins and the lower 4 bits (bits [3:0]) can be used as general-purpose input pins. (Bits [5:4] are not used.) Port F ...
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Register Address Name (base+) GPIOFDATA 0x03FC GPIOFDIR 0x0400 GPIOFFR1 0x0424 − 0x0428 GPIOFIS 0x0804 GPIOFIBE 0x0808 GPIOFIEV 0x080C GPIOFIE 0x0810 GPIOFRIS 0x0814 GPIOFMIS 0x0818 GPIOFIC 0x081C GPIOFODE 0x0C00 1. GPIOFDATA (Port F Data Register) Bit Bit Symbol − − [31:8] ...
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GPIOFFR1 (Port F Function Register 1) Bit Bit Symbol − [31:8] [7:6] PF7F1 to PF6F1 − [5:4] [3:0] PF3F1 to PF0F1 [Description] a. <PF7F1:PF6F1, PF7F3:PF0F1> Function register 1: Controls the function setting. 4. GPIOFIS (Port F Interrupt Select Register ...
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GPIOFIBE (Port F Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol − [31:8] [7] PF7IBE − [6:0] [Description] a. <PFF7IBE> Interrupt both-edge register: Selects the trigger edge from single edge and both-edge. 0y0: Single edge 0y1: ...
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GPIOFIE (Port F Interrupt Enable Register) Bit Bit Symbol − [31:8] [7] PF7IE [6:0] Reserved [Description] a. <PF7IE> Interrupt enable register: Enables or disables interrupts. 0y0: Disabled 0y1: Enabled 8. GPIOFRIS (Port F Interrupt Status Register (Raw)) Bit Bit ...
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GPIOFMIS (Port F Interrupt Status Register (Masked)) Bit Bit Symbol − [31:8] [7] PF7MIS − [6:0] [Description] a. <PF7MIS> Masked interrupt status register: Monitors the interrupt status after being masked by the interrupt register. 0y0: Not requested 0y1: Requested ...
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GPIOFODE (Port F Open-drain Output Enable Register) Bit Bit Symbol − [31:8] [7:6] PF7ODE to PF6ODE − [5:4] [3:0] PF3ODE to PF0ODE [Description] a. <PF7ODE to PF6ODE, PF3ODE to PF0ODE > Open-drain output enable register: Selects the output mode ...
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Port G Port G can be used as general-purpose input/output pins. Port G can also be used as SD host controller function pins (SDC0CLK, SDC0CD, SDC0WP, SDC0CMD, SDC0DAT3, SDC0DAT2, SDC0DAT1 and SDC0DAT0). General-purpose input setting Function Data Value GPIOGDATA ...
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GPIOGDATA (Port G Data Register) Bit Bit Symbol − − [31:8] [7:0] PG[7:0] R/W [Description] a. <PG[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOGDIR (Port G Data Direction Register) Bit ...
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Port H Port H can be used as general-purpose input/output pins. Port H can also be used as SD host controller function pins (SDC1CLK, SDC1CD, SDC1WP, SDC1CMD, SDC1DAT3, SDC1DAT2, SDC1DAT1 and SDC1DAT0). General-purpose input setting Function Data Value GPIOHDATA ...
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GPIOHDATA (Port H Data Register) Bit Bit Symbol − − [31:8] [7:0] PH[7:0] RW [Description] a. <PH[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOHDIR (Port H Data Direction Register) Bit ...
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Port J Port J can be used as general-purpose output pins. Port J can also be used as LCD controller function pins (LD15-LD8). General-purpose output setting Function Data Value GPIOJDATA General-purpose output * Bit 7 Bit 6 Bit 5 ...
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GPIOJDATA (Port J Data Register) Bit Bit Symbol − − [31:8] [7:0] PJ[7:0] R/W [Description] a. <PJ[7:0]> Data Register: Stores data. See notes on data registers for the bit mask function. 2. GPIOJFR1 (Port J Function Register 1) Bit ...
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Port K Port K can be used as general-purpose output pins. Port K can also be used as LCD controller function pins (LD23-LD16). General-purpose output settings Function Data Value GPIOKDATA General-purpose output * Bit 7 Bit 6 Bit 5 ...
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GPIOKDATA (Port K Data Regsiter) Bit Bit Symbol − − [31:8] [7:0] PK[7:0] R/W [Description] a. <PK[7:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOKFR1 (Port K Function Register 1) Bit ...
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Port L Port L can be used as general-purpose input/output pins. (Bits [7:5] are not used.) In addition, Port L can also be used as I I2S0CLK and I2S0WS) and SPI function (SP1DI, SP1DO, SP1CLK and SP1FSS) pins. General-purpose ...
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Register Address Name (base+) GPIOLDATA 0x03FC GPIOLDIR 0x0400 GPIOLFR1 0x0424 GPIOLFR2 0x0428 − 0x0804 − 0x0808 − 0x080C − 0x0810 − 0x0814 − 0x0818 − 0x081C − 0x0C00 1. GPIOLDATA (Port L Data Register) Bit Bit Symbol − − [31:8] ...
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GPIOLFR1 (Port L Function Register 1) Bit Bit Symbol − [31:8] − [7:5] [4:0] PL4F1 to PL0F1 [Description] a. <PL4F1 to PL0F1> Function register 1: Controls the function setting. 4. GPIOLFR2 (Port L Function Register 2) Bit Bit Symbol ...
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Port M Port M can be used as general-purpose input/output pins. (Bits [7:4] are not used.) Port M can also be used as I I2S1WS). General-purpose input setting Function Data Value GPIOMDATA General-purpose input * Bit 7 Bit 6 ...
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GPIOMDATA (Port M Data Register) Bit Bit Symbol − − [31:8] − − [7:4] [3:0] PM[3:0] R/W [Description] a. <PM[3:0]> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOMDIR (Port M Data ...
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Port N Port N can be used as general-purpose input/output pins. Port N can also be used as UART function (U0RTSn, U0DTRn, U0RIn, U0DSRn, U0DCDn, U0CTSn, U0RXD, U0TXD, SIR0IN, SIR0OUT) and interrupt function (INTD, INTE, INTF, INTG) pins. General-purpose ...
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Register Address Name (base+) GPIONDATA 0x03FC GPIONDIR 0x0400 GPIONFR1 0x0424 GPIONFR2 0x0428 GPIONIS 0x0804 GPIONIBE 0x0808 GPIONIEV 0x080C GPIONIE 0x0810 GPIONRIS 0x0814 GPIONMIS 0x0818 GPIONIC 0x081C − 0x0C00 1. GPIONDATA (Port N Data Register) Bit Bit Symbol − − [31:8] ...
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GPIONFR1 (Port N Function Register 1) Bit Bit Symbol − [31:8] [7:2] PN7F1 to PN2F1 [1] Reserved [0] PN0F1 [Description] a. <PN7F1 to PN2F1,PN0F1> Function register 1: Controls the function setting. 4. GPIONFR2 (Port N Function Register 2) Bit ...
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GPIONIS (Port N Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] [7:4] PN7IS to PN4IS [3:0] Reserved [Description] a. <PN7IS to PN4IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIONIBE (Port ...
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GPIONIEV (Port N Interrupt Select Register(“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] [7:4] PN7IEV to PN4IEV [3:0] Reserved [Description] a. <PN7IEV to PN4IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive ...
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GPIONRIS (Port N Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7:4] PN7RIS to PN4RIS − [3:0] [Description] a. <PN7RIS to PN4RIS> Interrupt raw status register: Monitors the interrupt status before being masked by the interrupt enable register. ...
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GPIONIC (Port N Interrupt Clear Register) Bit Bit Symbol − [31:8] [7:4] PN7IC to PN4IC − [3:0] [Description] a. <PN7IC to PN4IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear TENTATIVE Reset Type Value − Undefined Read ...
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Port P Port P can be used as general-purpose input/output pins. Port P can also be used as interrupt function pins (INT7 to INT0). General-purpose input and Interrupt settings Function Data Value General-purpose input GPIOPDATA Interrupt * Bit 7 ...
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GPIOPDATA (Port P Data Register) Bit Bit Symbol − − [31:8] [7:0] PP7 to PP0 R/W [Description] a. <PP7 to PP0> Data register: Stores data. See notes on data registers for the bit mask function. 2. GPIOPDIR (Port P ...
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GPIOPIBE (Port P Interrupt Select Register (Single edge and Both edge)) Bit Bit Symbol − [31:8] [7:0] PP7IBE to PP0IBE [Description] a. <PP7IBE to PP0IBE> Interrupt both-edge register: Selects single edge or both-edge. 0y0: Single edge 0y1: Both-edge 5. ...
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GPIOPRIS (Port P Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] [7:0] PP7RIS to PP0RIS [Description] a. <PP7RIS to PP0RIS > Interrupt raw status register: Monitors the interrupt status before masking. 0y0: Not requested 0y1: Requested 8. GPIOPMIS ...
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GPIOPIC (Port P Interrupt Clear Register) Bit Bit Symbol − [31:8] [7:0] PP7IC to PP0IC [Description] a. <PP7IC to PP0IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear TENTATIVE Reset Type Value − Undefined Read as undefined. ...
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Port R Bit 2 of Port R can be used as a general-purpose input/output pin and bits [0:1] can be used as general-purpose output pins. (Bits [7:3] are not used.) Port R can also be used as reset output ...
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Register Address Name (base+) GPIORDATA 0x03FC GPIORDIR 0x0400 GPIORFR1 0x0424 − 0x0428 GPIORFR2 0x0428 GPIORIS 0x0804 GPIORIBE 0x0808 GPIORIEV 0x080C GPIORIE 0x0810 GPIORRIS 0x0814 GPIORMIS 0x0818 GPIORIC 0x081C − 0x0C00 1. GPIORDATA (Port R Data Register) Bit Bit Symbol − ...
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GPIORFR1 (Port R Function Register 1) Bit Bit Symbol − [31:8] − [7:3] [2:1] Reserved [0] PR0F1 [Description] a. <PR0F1> Function register 1: Controls the function setting. 4. GPIORFR2 (Port R Function Register 2) Bit Bit Symbol − [31:8] ...
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GPIORIS (Port R Interrupt Select Register (Level and Edge)) Bit Bit Symbol − [31:8] − [7:3] [2] PR2IS [1:0] Reserved [Description] a. <PR2IS> Interrupt sensitivity register: Selects edge-sensitive or level-sensitive. 0y0: Edge-sensitive 0y1: Level-sensitive 6. GPIORIBE (Port R Interrupt ...
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GPIORIEV (Port R Interrupt Select Register(“Falling edge/Low level” and “Rising edge/High level”)) Bit Bit Symbol − [31:8] − [7:3] [2] PR2IEV [1:0] Reserved [Description] a. <PR2IEV> Interrupt event register: Selects falling edge or rising edge for edge-sensitive interrupts, and ...
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GPIORRIS (Port R Interrupt Status Register (Raw)) Bit Bit Symbol − [31:8] − [7:3] [2] PR2RIS − [1:0] [Description] a. <PR2RIS > Interrupt raw status register: Monitors the interrupt status before masking. 0y0: Not requested 0y1: Requested 10. GPIORMIS ...
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GPIORIC (Port R Interrupt Clear Register) Bit Bit Symbol − [31:8] − [7:3] [2] PR2IC − [1:0] [Description] a. <PR2IC> Interrupt clear register: Clears edge-sensitive interrupts. 0y0: Invalid 0y1: Clear request TENTATIVE Reset Type Value − Undefined Read as ...
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Port T Port T can be used as general-purpose input/output pins. Port T can also be used as USB external clock input (X1USB), UART function (U1CTSn, U1RXD, U1TXD), and SSP function (SP0DI, SP0DO, SP0CLK, SP0FSS) pins. General-purpose input setting ...
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Register Address Name (base+) GPIOTDATA 0x03FC GPIOTDIR 0x0400 GPIOTFR1 0x0424 − 0x0428 − 0x0804 − 0x0808 − 0x080C − 0x0810 − 0x0814 − 0x0818 − 0x081C − 0x0C00 1. GPIOTDATA (Port T Data Register) Bit Bit Symbol − − [31:8] ...
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GPIOTFR1 (Port T Function Register 1) Bit Bit Symbol − [31:8] [7:0] PT7F1 to PT0F1 [Description] a. <PT7F1 to PT0F1> Function register 1: Controls the function setting. TENTATIVE Reset Type Value − Undefined Read as undefined. Written as zero. ...
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Notes • Procedure for using the interrupt function Interrupts can be detected in various modes depending on the sensitivity setting. The following procedure should be observed when the interrupt function is enabled (GPIOnIE = 1) or the interrupt mode ...
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MPMC This LSI contains two types of memory controller with different specifications. Depending on the connected external memory, one of two types of controllers (MPMC0/MPMC1) can be selected by setting the external pin SELMEMC (port SN0). By setting the ...
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The following shows differences in supported memory between MPMC0 and MPMC1. Select MPMC0 or MPMC1 depending on SDRAM to use. MPMC0: 32-bit/16-bit Standard type SDR SDRAM 32-bit/16-bit Mobile type SDR SDRAM 32-bit/16-bit NOR Flash (Separate bus only) 32-bit/16-bit SRAM (Separate ...
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According to the voltage of the connected external memory, set pin and register as follows. Note: The two memory controllers cannot be used by dynamically switching between them. The memory controller to be used must be fixed. Mode setting pin ...
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EBI (External Bus Interface) Memory controllers (MPMC0 and MPMC1) have a built-in SMC (Static Memory Controller) circuit and DMC (Dynamic Memory Controller) circuit. The external bus of SMC is used also as the external bus of DMC in the ...