M30620SPGP#U3C Renesas Electronics America, M30620SPGP#U3C Datasheet - Page 65
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M30620SPGP#U3C
Manufacturer Part Number
M30620SPGP#U3C
Description
IC M16C MCU ROMLESS 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620SPGP#U3C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
50
Program Memory Type
ROMless
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ03B0001-0241
Figure 5.10
Memory Expansion Mode, Microprocessor Mode
(For 1- or 2-wait setting, external area access and multiplex bus selection )
Read timing
Write timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
WR,WRL,
WRH
Measuring conditions
· V
· Input timing voltage : V
· Output timing voltage : V
CC1
Jan 10, 2006
=V
CC2
Timing Diagram (8)
=5V
t
d(BCLK-ALE)
t
d(BCLK-CS)
t
d(BCLK-ALE)
(0.5×t
25ns.max
t
t
t
25ns.max
t
25ns.max
t
d(BCLK-AD)
d(BCLK-CS)
25ns.max
d(BCLK-AD)
d(AD-ALE)
(0.5×t
25ns.max
25ns.max
d(AD-ALE)
Page 63 of 96
cyc
cyc
-25)ns.min
IL
-25)ns.min
Address
Address
=0.8V, V
OL
=0.4V, V
t
t
h(BCLK-ALE)
h(BCLK-ALE)
−4ns.min
−4ns.min
IH
=2.0V
OH
=2.4V
t
d(BCLK-RD)
t
t
d(BCLK-DB)
h(ALE-AD)
(0.5×t
t
40ns.max
25ns.max
25ns.max
d(BCLK-WR)
t
d(AD-WR)
0ns.min
t
t
0ns.min
cyc
dZ(RD-AD)
8ns.max
d(AD-RD)
t
-15)ns.min
cyc
t
cyc
(1.5×t
(1.5×t
Data output
t
t
d(DB-WR)
cyc
ac3(RD-DB)
cyc
-40)ns.min
-45)ns.max
t
Data input
su(DB-RD)
40ns.min
(0.5×t
(0.5×t
cyc
V
cyc
t
-10)ns.min
t
(0.5×t
h(RD-CS)
(0.5×t
t
h(BCLK-WR)
CC1
h(BCLK-RD)
-10)ns.min
(0.5×t
t
h(WR-CS)
t
0ns.min
0ns.min
t
t
5. Electrical Characteristics
h(RD-AD)
t
cyc
h(WR-AD)
h(RD-DB)
0ns.min
cyc
h(WR-DB)
cyc
-10)ns.min
-10)ns.min
-10)ns.min
=V
t
t
CC2
h(BCLK-AD)
h(BCLK-AD)
t
h(BCLK-CS)
t
4ns.min
4ns.min
h(BCLK-CS)
t
4ns.min
4ns.min
h(BCLK-DB)
4ns.min
Address
Address
=5V