C8051F002-GQ Silicon Laboratories Inc, C8051F002-GQ Datasheet - Page 134
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C8051F002-GQ
Manufacturer Part Number
C8051F002-GQ
Description
IC 8051 MCU 32K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F00xr
Specifications of C8051F002-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 4x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
8
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F005DK
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 12-bit
On-chip Dac
2-ch x 12-bit
Package
32LQFP
Device Core
8051
Family Name
C8051F0xx
Maximum Speed
20 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1246 - DEV KIT F300/301/302/303/304/305
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1186
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F002-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F002-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
18.1.3. Mode 2: 9-Bit UART, Fixed Baud Rate
Mode 2 provides asynchronous, full-duplex communication using a total of eleven bits per data byte: a start bit, 8
data bits (LSB first), a programmable ninth data bit, and a stop bit (see timing diagram in Figure 18.6). On transmit,
the ninth data bit is determined by the value in TB8 (SCON.3). It can be assigned the value of the parity flag P in
the PSW or used in multiprocessor communications. On receive, the ninth data bit goes into RB8 (SCON.2) and the
stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF register. The TI Transmit Interrupt
Flag (SCON.1) is set at the end of the transmission (the beginning of the stop-bit time). Data reception can begin
any time after the REN Receive Enable bit (SCON.4) is set to logic 1. After the stop bit is received, the data byte
will be loaded into the SBUF receive register if the following conditions are met: RI must be logic 0, and if SM2 is
logic 1, the 9
If these conditions are met, the eight bits of data are stored in SBUF, the ninth bit is stored in RB8 and the RI flag is
set. If these conditions are not met, SBUF and RB8 will not be loaded and the RI flag will not be set. An interrupt
will occur if enabled when either TI or RI are set.
The baud rate in Mode 2 is a direct function of the system clock frequency as follows:
The SMOD bit (PCON.7) selects whether to divide SYSCLK by 32 or 64. In the formula, 2 is raised to the power
SMOD, resulting in a baud rate of either 1/32 or 1/64 of the system clock frequency. On reset, the SMOD bit is
logic 0, thus selecting the lower speed baud rate by default.
18.1.4. Mode 3: 9-Bit UART, Variable Baud Rate
Mode 3 is the same as Mode 2 in all respects except the baud rate is variable. The baud rate is determined in the
same manner as for Mode 1. Mode 3 operation transmits 11 bits: a start bit, 8 data bits (LSB first), a programmable
ninth data bit, and a stop bit. Timer 1 or Timer 2 overflows generate the baud rate just as with Mode 1. In
summary, Mode 3 transmits using the same protocol as Mode 2 but with Mode 1 baud rate generation.
SPACE
MARK
BIT TIMES
BIT SAMPLING
th
bit must be logic 1.
START
BIT
Figure 18.6. UART Modes 2 and 3 Timing Diagram
D0
D1
Mode 2 Baud Rate = 2
D2
Rev. 1.7
D3
SMOD
D4
* (SYSCLK / 64).
D5
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
D6
D7
D8
STOP
BIT
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