MC9S12C32VFAE16 Freescale Semiconductor, MC9S12C32VFAE16 Datasheet - Page 427

• Manufacturer Part Number: MC9S12C32VFAE16
• Description: IC MCU 32K FLASH 16MHZ 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12C32VFAE16

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• For Use With: CML12C32SLK - KIT STUDENT LEARNING 16BIT HCS12
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Data reception is double buffered. Data is shifted serially into the SPI shift register during the transfer and
is transferred to the parallel SPI Data Register after the last bit is shifted in.
After the 16th (last) SCK edge:
Figure 14-9
CPOL = 0 and CPOL = 1. The diagram may be interpreted as a master or slave timing diagram because
the SCK, MISO, and MOSI pins are connected directly between the master and the slave. The MISO signal
is the output from the slave and the MOSI signal is the output from the master. The SS pin of the master
must be either high or reconfigured as a general-purpose output not affecting the SPI.
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the
SPI Data Register is not transmitted, instead the last received byte is transmitted. If the SS line is deasserted
for at least minimum idle time (half SCK cycle) between successive transmissions then the content of the
SPI Data Register is transmitted.
Freescale Semiconductor
•
•
End of Idle State
SCK Edge Nr.
MSB first (LSBFE = 0):
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
t
MOSI pin
MISO pin
Data that was previously in the master SPI Data Register should now be in the slave data register
and the data that was in the slave data register should be in the master.
The SPIF flag in the SPI Status Register is set indicating that the transfer is complete.
LSB first (LSBFE = 1):
L
T
I
L
, t
= Minimum idling time between transfers (minimum SS high time)
= Minimum leading time before the first SCK edge
= Minimum trailing time after the last SCK edge
T
, and t
is a timing diagram of an SPI transfer where CPHA = 0. SCK waveforms are shown for
I
are guaranteed for the master mode and required for the slave mode.
tL
MSB
LSB
1
Figure 14-9. SPI Clock Format 0 (CPHA = 0)
2
Begin
Bit 6
Bit 1
3
MC9S12C-Family / MC9S12GC-Family
4
Bit 5
Bit 2
5
6
Bit 4
Bit 3
Rev 01.24
7
Transfer
8
Chapter 14 Serial Peripheral Interface (SPIV3) Block Description
Bit 3
Bit 4
9
10
Bit 2
Bit 5
11
12
Bit 1
Bit 6
13 14
End
MSB
15
LSB
16
Minimum 1/2 SCK
tT
for t
Begin of Idle State
T
tI
, t
l
, t
L
tL
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