C8051F340-GQ Silicon Laboratories Inc, C8051F340-GQ Datasheet
C8051F340-GQ
Specifications of C8051F340-GQ
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C8051F340-GQ Summary of contents
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... Supports all USB and UART modes - External Oscillator: Crystal, RC clock ( Pin modes) - Low Frequency (80 kHz) Internal Oscillator - Can switch between clock sources on-the-fly Packages - 48-pin TQFP (C8051F340/1/4/5/8) - 32-pin LQFP (C8051F342/3/6/7/9) Temperature Range: –40 to +85 °C ANALOG DIGITAL I/O PERIPHERALS UART0 UART1 + ...
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... C8051F340/1/2/3/4/5/6/7/8 OTES 2 Rev. 1.1 ...
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... Programmable Counter Array ........................................................................... 34 1.9. 10-Bit Analog to Digital Converter..................................................................... 35 1.10.Comparators..................................................................................................... 36 2. Absolute Maximum Ratings .................................................................................. 37 3. Global DC Electrical Characteristics .................................................................... 38 4. Pinout and Package Definitions............................................................................ 41 5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7 Only)............................................... 49 5.1. Analog Multiplexer ............................................................................................ 50 5.2. Temperature Sensor ......................................................................................... 51 5.3. Modes of Operation .......................................................................................... 53 5.3.1. Starting a Conversion............................................................................... 53 5.3.2. Tracking Modes........................................................................................ 54 5 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 9.2.7. Register Descriptions ............................................................................... 94 9.3. Interrupt Handler ............................................................................................... 96 9.3.1. MCU Interrupt Sources and Vectors ........................................................ 96 9.3.2. External Interrupts .................................................................................... 96 9.3.3. Interrupt Priorities ..................................................................................... 97 9.3.4. Interrupt Latency ...................................................................................... 97 9.3.5. Interrupt Register Descriptions................................................................. 98 9.4. Power Management Modes ............................................................................ 105 9.4.1. Idle Mode................................................................................................ 105 9.4.2. Stop Mode .............................................................................................. 105 10. Prefetch Engine .................................................................................................... 109 11 ...
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... OUT Transactions............................................................... 194 16.11.Configuring Endpoints1-3 ............................................................................. 196 16.12.Controlling Endpoints1-3 IN.......................................................................... 196 16.12.1.Endpoints1-3 IN Interrupt or Bulk Mode............................................... 196 16.12.2.Endpoints1-3 IN Isochronous Mode..................................................... 197 16.13.Controlling Endpoints1-3 OUT...................................................................... 199 16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode........................................... 199 16.13.2.Endpoints1-3 OUT Isochronous Mode................................................. 200 17. SMBus ................................................................................................................... 205 17.1.Supporting Documents ................................................................................... 206 C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 5 ...
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... UART0.................................................................................................................... 223 18.1.Enhanced Baud Rate Generation................................................................... 224 18.2.Operational Modes ......................................................................................... 224 18.2.1.8-Bit UART ............................................................................................. 225 18.2.2.9-Bit UART ............................................................................................. 226 18.3.Multiprocessor Communications .................................................................... 226 19. UART1 (C8051F340/1/4/5/8 Only) ........................................................................ 231 19.1.Baud Rate Generator ..................................................................................... 232 19.2.Data Format.................................................................................................... 233 19.3.Configuration and Operation .......................................................................... 234 19.3.1.Data Transmission ................................................................................. 234 19.3.2.Data Reception ...................................................................................... 234 19.3.3.Multiprocessor Communications ............................................................ 235 20 ...
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... Pulse Width Modulator Mode....................................................... 283 22.3.Watchdog Timer Mode ................................................................................... 284 22.3.1.Watchdog Timer Operation .................................................................... 284 22.3.2.Watchdog Timer Usage ......................................................................... 285 22.4.Register Descriptions for PCA........................................................................ 286 23. C2 Interface ........................................................................................................... 291 23.1.C2 Interface Registers.................................................................................... 291 23.2.C2 Pin Sharing ............................................................................................... 293 Document Change List............................................................................................. 294 Contact Information.................................................................................................. 296 C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 7 ...
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... C8051F340/1/2/3/4/5/6/7/8 OTES 8 Rev. 1.1 ...
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... Figure 1.3. C8051F348 Block Diagram .................................................................... 25 Figure 1.4. C8051F349 Block Diagram .................................................................... 26 Figure 1.5. On-Chip Clock and Reset ...................................................................... 28 Figure 1.6. On-Chip Memory Map for 64kB Devices (C8051F340/2/4/6) ................ 29 Figure 1.7. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) ......... 30 Figure 1.8. USB Block Diagram ............................................................................... 31 Figure 1.9. Digital Crossbar Diagram ....................................................................... 33 Figure 1 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Figure 9.1. CIP-51 Block Diagram............................................................................ 81 Figure 9.2. On-Chip Memory Map for 64 kB Devices (C8051F340/2/4/6) ............... 87 Figure 9.3. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) ......... 88 10. Prefetch Engine 11. Reset Sources Figure 11.1. Reset Sources.................................................................................... 111 Figure 11.2. Power-On and VDD Monitor Reset Timing ........................................ 112 12 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 11 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Figure 22.9. PCA 16-Bit PWM Mode...................................................................... 283 Figure 22.10. PCA Module 4 with Watchdog Timer Enabled ................................. 284 23. C2 Interface Figure 23.1. Typical C2 Pin Sharing....................................................................... 293 12 Rev. 1.1 ...
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... N : OTES C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 13 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 14 Rev. 1.1 ...
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... Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ....................................................... 38 Table 3.2. Index to Electrical Characteristics Tables ............................................... 40 4. Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 ............................... 41 Table 4.2. TQFP-48 Package Dimensions .............................................................. 45 Table 4.3. LQFP-32 Package Dimensions .............................................................. 47 5. 10-Bit ADC (ADC0, C8051F340/1/2/3/4/5/6/7 Only) Table 5 ...
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... Table 17.4. SMBus Status Decoding ..................................................................... 221 18. UART0 Table 18.1. Timer Settings for Standard Baud Rates Using The Internal Oscillator ... 230 19. UART1 (C8051F340/1/4/5/8 Only) Table 19.1. Baud Rate Generator Settings for Standard Baud Rates ................... 232 20. Enhanced Serial Peripheral Interface (SPI0) Table 20.1. SPI Slave Timing Parameters ............................................................ 253 21 ...
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... SFR Definition 13.2. EMI0CF: External Memory Configuration . . . . . . . . . . . . . . . . . 131 SFR Definition 13.3. EMI0TC: External Memory Timing Control . . . . . . . . . . . . . . . . 136 SFR Definition 14.1. OSCICN: Internal H-F Oscillator Control . . . . . . . . . . . . . . . . . . 146 SFR Definition 14.2. OSCICL: Internal H-F Oscillator Calibration . . . . . . . . . . . . . . . 147 C8051F340/1/2/3/4/5/6/7/8/9 Monitor Control . . . . . . . . . . . . . . . . . . . . . . . . . 113 DD Rev. 1.1 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control . . . . . . . . . . . . . . . . . . 148 SFR Definition 14.4. OSCXCN: External Oscillator Control . . . . . . . . . . . . . . . . . . . . 151 SFR Definition 14.5. CLKMUL: Clock Multiplier Control . . . . . . . . . . . . . . . . . . . . . . . 152 SFR Definition 14.6. CLKSEL: Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 SFR Definition 15.1. XBR0: Port I/O Crossbar Register 163 SFR Definition 15 ...
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... SFR Definition 22.2. PCA0MD: PCA Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 SFR Definition 22.3. PCA0CPMn: PCA Capture/Compare Mode . . . . . . . . . . . . . . . 288 SFR Definition 22.4. PCA0L: PCA Counter/Timer Low Byte . . . . . . . . . . . . . . . . . . . 289 SFR Definition 22.5. PCA0H: PCA Counter/Timer High Byte . . . . . . . . . . . . . . . . . . . 289 SFR Definition 22.6. PCA0CPLn: PCA Capture Module Low Byte . . . . . . . . . . . . . . . 289 C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 19 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 22.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 290 C2 Register Definition 23.1. C2ADD: C2 Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 C2 Register Definition 23.2. DEVICEID: C2 Device 291 C2 Register Definition 23.3. REVID: C2 Revision 292 C2 Register Definition 23.4. FPCTL: C2 Flash Programming Control . . . . . . . . . . . . 292 C2 Register Definition 23.5. FPDAT: C2 Flash Programming Data . . . . . . . . . . . . . . 292 20 Rev ...
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... For voltages above 3.6 V, the on-chip Voltage Regulator must be used. A minimum of 3 required for USB communication. The Port I/O and /RST pins are tolerant of input signals C8051F340/1/2/3/ 4/5/6/7/8/9 devices are available in 48-pin TQFP or 32-pin LQFP packages. See Table 1.1, “Product Selec- tion Guide,” ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 1.1. Product Selection Guide C8051F340-GQ 48 64k 4352 C8051F341-GQ 48 32k 2304 C8051F342-GQ 48 64k 4352 C8051F343-GQ 48 32k 2304 C8051F344-GQ 25 64k 4352 C8051F345-GQ 25 32k 2304 C8051F346-GQ 25 64k 4352 C8051F347-GQ 25 32k 2304 C8051F348-GQ 25 32k 2304 C8051F349-GQ 25 32k 2304 — — Rev. 1.1 2 TQFP48 ...
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... Internal Oscillator Clock Low Freq. Recovery Oscillator USB Peripheral D+ Controller Full / Low D- Speed 1k Byte Transceiver VBUS RAM Figure 1.1. C8051F340/1/4/5 Block Diagram C8051F340/1/2/3/4/5/6/7/8/9 Port I/O Configuration Digital Peripherals Port 0 UART0 Drivers UART1 Timers 0, 1, Priority 2, 3 Port 1 Crossbar Drivers Decoder PCA/WDT ...
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... C8051F340/1/2/3/4/5/6/7/8/9 C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 64/32 kB ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net Voltage VREG 4/2 kB XRAM Regulator GND System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator ...
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... Internal Oscillator Clock Low Freq. Recovery Oscillator USB Peripheral D+ Controller Full / Low D- Speed Transceiver VBUS Figure 1.3. C8051F348 Block Diagram C8051F340/1/2/3/4/5/6/7/8/9 Port I/O Configuration Digital Peripherals UART0 UART1 Timers 0, 1, Priority 2, 3 Crossbar Decoder PCA/WDT SMBus SPI Crossbar Control SFR Bus ...
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... C8051F340/1/2/3/4/5/6/7/8/9 C2D Debug / Programming Hardware C2CK/RST Reset CIP-51 8051 Controller Core Power-On Reset 32 kB ISP FLASH Supply Program Memory Monitor VDD 256 Byte RAM Power Net Voltage VREG 2 kB XRAM Regulator GND System Clock Setup XTAL1 External Oscillator XTAL2 Internal Oscillator ...
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... Number of Instructions 26 1.1.3. Additional Features The C8051F340/1/2/3/4/5/6/7/8/9 SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 16 interrupt sources into the CIP-51 (as opposed to 7 for the stan- dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by the MCU, giving it more effective throughput ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Comparator 0 Px.x Px.x Internal LF Oscillator Internal HF Oscillator System Clock Clock Multiplier External XTAL1 Oscillator Clock Select XTAL2 Drive Figure 1.5. On-Chip Clock and Reset 28 VDD Supply Monitor Enable + - Power On Reset + - C0RSEF Missing Clock Detector (one- PCA shot) Software Reset (SWRSF) ...
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... On-chip XRAM is also included for the entire device family. The 64 k FLASH devices (C8051F340/2/4/6) have XRAM space. The 32 k Flash devices (C8051F341/3/5/7/8/9) have XRAM space. A separate 1 k Bytes of USB FIFO RAM is also included on all devices. See Figure 1.6 for the MCU system memory map of the 64k Flash devices ...
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... C8051F340/1/2/3/4/5/6/7/8/9 PROGRAM/DATA MEMORY (FLASH) 0x7FFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 1.7. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) 30 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) (Direct Addressing Only) 0x80 0x7F (Direct and Indirect ...
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... The USB Transceiver is USB 2.0 compliant, and includes on-chip matching and pull-up resistors. The pull-up resistors can be enabled/disabled in software, and will appear on the pin according to the software-selected speed setting (Full or Low Speed). Transceiver VDD D+ D- Figure 1.8. USB Block Diagram C8051F340/1/2/3/4/5/6/7/8/9 Serial Interface Engine (SIE) Endpoint0 IN/OUT USB Data Control, Endpoint1 ...
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... It also has a target application board with the C8051F340 MCU installed, the necessary cables for connection to a PC, and a wall-mount power supply. The development kit contents may also be used to program and debug the device on the production PCB using the appropriate connections for the programming pins ...
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... Programmable Digital I/O and Crossbar C8051F340/1/4/5/8 devices include 40 I/O pins (five byte-wide Ports); C8051F342/3/6/7/9 devices include 25 I/O pins (three byte-wide Ports, and a 1-bit-wide Port). The C8051F340/1/2/3/4/5/6/7/8/9 Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be configured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain out- put. The “ ...
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... C8051F340/1/2/3/4/5/6/7/8/9 1.7. Serial Ports The C8051F340/1/2/3/4/5/6/7/8/9 Family includes an SMBus/I2C interface, full-duplex UARTs, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the CIP-51's interrupts, thus requiring very little CPU intervention. 1.8. Programmable Counter Array An on-chip Programmable Counter/Timer Array (PCA) is included in addition to the four 16-bit general pur- pose counter/timers ...
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... Analog to Digital Converter The C8051F340/1/2/3/4/5/6/7 devices include an on-chip 10-bit SAR ADC with a true differential input mul- tiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit linearity with an INL of ±1LSB. The ADC system includes a configurable analog multiplexer that selects both positive and negative ADC inputs ...
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... C8051F340/1/2/3/4/5/6/7/8/9 1.10. Comparators C8051F340/1/2/3/4/5/6/7/8/9 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output ...
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... Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. C8051F340/1/2/3/4/5/6/7/8/9 Conditions Min –55 – ...
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... Table 3.1. Global DC Electrical Characteristics –40 to +85 °C, 25 MHz System Clock unless otherwise specified. Parameter 1 Digital Supply Voltage Digital Supply RAM Data Retention Voltage 2 C8051F340/1/2/3 SYSCLK (System Clock) C8051F344/5/6/7/8/9 Specified Operating Temperature Range Digital Supply Current - CPU Active (Normal Mode, accessing Flash ...
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... Other electrical characteristics tables are found in the data sheet section corresponding to the associated peripherals. For more information on electrical characteristics for a specific peripheral, refer to the page indicated in Table 3.2. C8051F340/1/2/3/4/5/6/7/8/9 Conditions Min = 3.3 V, SYSCLK < 1 MHz, = 3.3 V, SYSCLK > 1 MHz, = 3.6 V, SYSCLK < ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 3.2. Index to Electrical Characteristics Tables Table Title ADC0 Electrical Characteristics Voltage Reference Electrical Characteristics Comparator Electrical Characteristics Voltage Regulator Electrical Specifications Reset Electrical Characteristics Flash Electrical Characteristics AC Parameters for External Memory Interface Oscillator Electrical Characteristics Port I/O DC Electrical Characteristics ...
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... Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 Pin Numbers Name 48-pin 32-pin Power In DD GND 7 3 /RST C2CK C2D C2D REGIN 11 7 Power Regulator Input. This pin is the input to the on-chip volt- VBUS P0.4 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 (Continued) Pin Numbers Name 48-pin 32-pin Type Description D I/O or Port 1.0. See Section I/O or Port 1. I/O or Port 1. I/O or Port 1. I/O or Port 1. I/O or Port 1.5. ...
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... Table 4.1. Pin Definitions for the C8051F340/1/2/3/4/5/6/7/8/9 (Continued) Pin Numbers Name Type 48-pin 32-pin C8051F340/1/2/3/4/5/6/7/8/9 Description Port 3.3. Port 3.4. Port 3.5. Port 3.6. Port 3.7. Port 4.0. See ...
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... C8051F340/1/2/3/4/5/6/7/8/9 P0.5 1 P0.4 2 P0.3 3 P0.2 4 P0.1 5 C8051F340/1/4/5/8 P0.0 6 GND VDD 10 REGIN 11 VBUS 12 Figure 4.1. TQFP-48 Pinout Diagram (Top View) 44 Top View Rev. 1.1 P2.2 36 P2.3 35 P2.4 34 P2.5 33 P2.6 32 P2.7 31 P3.0 30 P3.1 29 P3.2 28 P3.3 27 P3.4 26 P3.5 25 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 4.2. TQFP-48 Package Dimensions Dimension Min A — A1 0.05 A2 0.95 b 0. 0.45 aaa bbb ccc ddd θ 0° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation ABC. ...
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... C8051F340/1/2/3/4/5/6/7/8/9 P0.1 1 P0.0 2 GND VDD 6 REGIN 7 VBUS 8 Figure 4.3. LQFP-32 Pinout Diagram (Top View) 46 C8051F342/3/6/7/9 Top View Rev. 1.1 P1 P1.3 P1.4 22 P1 P1.7 P2.0 18 P2.1 17 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 4.3. LQFP-32 Package Dimensions Dimension Min A — A1 0.05 A2 1.35 b 0. 0.45 aaa bbb ccc ddd θ 0° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MS-026, variation BBA. ...
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... C8051F340/1/2/3/4/5/6/7/8 OTES 48 Rev. 1.1 ...
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... ADC (ADC0, C8051F340/1/2/3/4/5/6/7 Only) The ADC0 subsystem for the C8051F340/1/2/3/4/5/6/7/8/9 consists of two analog multiplexers (referred to collectively as AMUX0), and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window detector. The AMUX0, data conversion modes, and window detector are all configured under software control via the Special Function Registers shown in Figure 5.1. ...
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... C8051F340/1/2/3/4/5/6/7/8/9 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. The positive input (AIN+) can be connected to individual Port pins, the on-chip temperature sensor, or the positive power supply (V input (AIN-) can be connected to individual Port pins, VREF, or GND. When GND is selected as the neg- ative input, ADC0 operates in Single-ended Mode ...
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... Step 4. Calculate the offset characteristics, and store this value in non-volatile memory for use with subsequent temperature sensor measurements. Figure 5.3 shows the typical temperature sensor error assuming a 1-point calibration at 25 °C. Note that parameters which affect ADC measurement, in particular the voltage reference value, will also affect temperature measurement. C8051F340/1/2/3/4/5/6/7/8/9 = (Gain x Temp ) + ...
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... C8051F340/1/2/3/4/5/6/7/8/9 5.0 0 4.0 0 3.0 0 2.0 0 1.0 0 0.0 0 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration (VREF = 2. 40.0 0.0 20 Temperature (degrees C) Rev. 1.1 5.0 0 4.0 0 3.0 0 2.0 0 1.0 0 0.0 60.0 80 -1.00 -2.00 -3.00 -4.00 -5.00 ...
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... CNVSTR input is used as the ADC0 conversion source, the associated Port pin should be skipped by the Digital Crossbar. To configure the Crossbar to skip a pin, set the corresponding bit in the PnSKIP register to ‘1’. See Section “15. Port Input/Output” on page 157 C8051F340/1/2/3/4/5/6/7/8/9 for timer configuration. for details on Port I/O configuration. Rev. 1.1 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 5.3.2. Tracking Modes The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0 input is continuously tracked, except when a conversion is in progress. When the AD0TM bit is logic 1, ADC0 operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a track- ing period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR signal is used to initi- ate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR is low ...
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... ADC resolution in bits (10). Differential Mode MUX Select Px MUX Input MUX SAMPLE Px MUX MUX Select Figure 5.5. ADC0 Equivalent Input Circuits C8051F340/1/2/3/4/5/6/7/8/9 reduces See Table 5.1 for ADC0 minimum TOTAL MUX n ⎛ ⎞ 2 × ------ - ⎝ ⎠ TOTAL SAMPLE SA Single-Ended Mode MUX Select Px ...
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... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select Bit7 Bit6 Bit5 Bits7–5: UNUSED. Read = 000b; Write = don’t care. Bits4–0: AMX0P4–0: AMUX0 Positive Input Selection AMX0P4-0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 Bit3 Bit2 ADC0 Negative Input ADC0 Negative Input (32-pin Package) (48-pin Package) P1.0 P1.1 P1.2 P1.3 P1.4 P1 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5 ...
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... Tracking initiated on overflow of Timer 1 and lasts 3 SAR clocks, followed by conversion. 100: ADC0 tracks only when CNVSTR input is logic low; conversion starts on rising CNVSTR edge. 101: Tracking initiated on overflow of Timer 3 and lasts 3 SAR clocks, followed by conversion. 11x: Reserved. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W ...
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... C8051F340/1/2/3/4/5/6/7/8/9 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 conversion results to user-programmed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster sys- tem response times ...
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... Bits7–0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Low byte of ADC0 Less-Than Data Word. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 Bit3 Bit2 Bit1 R/W ...
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... C8051F340/1/2/3/4/5/6/7/8/9 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer value ...
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... ADC0LTH:ADC0LTL 0x0FC0 0x0000 VREF x (-1/512) 0xFFC0 ADC0GTH:ADC0GTL 0xFF80 AD0WINT not affected 0x8000 -VREF Figure 5.9. ADC Window Compare Example: Left-Justified Differential Data C8051F340/1/2/3/4/5/6/7/8/9 ADC0H:ADC0L Input Voltage (Px.x - Px.x) VREF x (511/512) 0x01FF 0x0041 VREF x (64/512) 0x0040 0x003F AD0WINT=1 0x0000 VREF x (-1/512) ...
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... C8051F340/1/2/3/4/5/6/7/8/9 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V, –40 to +85 °C unless otherwise specified DD Parameter Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic Performance (10 kHz sine-wave Single-ended input below Full Scale, 200 ksps) Signal-to-Noise Plus Distortion ...
Page 65
... Voltage Reference (C8051F340/1/2/3/4/5/6/7 Only) The Voltage reference MUX on C8051F340/1/2/3/4/5/6/7/8/9 devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator, or the power supply voltage V (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the reference source. For the internal reference or an external source, REFSL should be set to ‘0’; For V source, REFSL should be set to ‘ ...
Page 66
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R Bit7 Bit6 Bit5 Bits7–3: UNUSED. Read = 00000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF pin used as voltage reference. ...
Page 67
... Comparators C8051F340/1/2/3/4/5/6/7/8/9 devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 7.1, where “n” is the comparator number (0 or 1). The two Comparators operate identically with the following exceptions: (1) Their input selections differ, and (2) Comparator0 can be used as a reset source. For input selection details, refer to SFR Definition 7.2 and SFR Definition 7 ...
Page 68
... C8051F340/1/2/3/4/5/6/7/8/9 CPTnMX Comparator outputs can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, Comparator outputs are available asynchronous or synchronous to the system clock; the asynchronous output is available even in STOP mode (with no system clock active). When dis- abled, the Comparator output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic low state, and supply current falls to less than 100 nA ...
Page 69
... Once set, these bits remain set until cleared by software. The output state of the Comparator can be obtained at any time by reading the CPnOUT bit. The Comparator is enabled by setting the CPnEN bit to ‘1’, and is disabled by clearing this bit to ‘0’. C8051F340/1/2/3/4/5/6/7/8/9 OUT Negative Hysteresis ...
Page 70
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0–. 1: Voltage on CP0+ > CP0–. Bit5: CP0RIF: Comparator0 Rising-Edge Flag. ...
Page 71
... These bits select which Port pin is used as the Comparator0 positive input. CMX0P1 CMX0P1 CMX0P0 Note that the port pins used by the comparator depend on the package type (32-pin or 48-pin). C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W - CMX0P2 CMX0P1 CMX0P0 00000000 Bit4 Bit3 Bit2 Bit1 Negative Input Negative Input ...
Page 72
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7–6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator0 Rising-Edge Interrupt Enable. 0: Comparator0 rising-edge interrupt disabled. 1: Comparator0 rising-edge interrupt enabled. Bit4: CP0FIE: Comparator0 Falling-Edge Interrupt Enable. ...
Page 73
... Positive Hysteresis = 5 mV. 10: Positive Hysteresis = 10 mV. 11: Positive Hysteresis = 20 mV. Bits1–0: CP1HYN1–0: Comparator1 Negative Hysteresis Control Bits. 00: Negative Hysteresis Disabled. 01: Negative Hysteresis = 5 mV. 10: Negative Hysteresis = 10 mV. 11: Negative Hysteresis = 20 mV. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W CP1FIF CP1HYP1 CP1HYP0 CP1HYN1 CP1HYN0 00000000 Bit4 Bit3 Bit2 Rev ...
Page 74
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W R/W R/W - CMX1N2 CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0b, Write = don’t care. Bits6–4: CMX1N2–CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin is used as the Comparator1 negative input. ...
Page 75
... Bits1–0: CP1MD1–CP1MD0: Comparator1 Mode Select. These bits select the response time for Comparator1. Mode CP1MD1 CP1MD0 See Table 7.1 for response time parameters. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R CP1MD1 CP1MD0 00000010 Bit4 Bit3 Bit2 Bit1 CP1 Response Time* 0 Fastest Response ...
Page 76
... C8051F340/1/2/3/4/5/6/7/8/9 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter CP0+ – CP0– = 100 mV Response Time: Mode 0, Vcm* = 1.5 V CP0+ – CP0– = –100 mV CP0+ – CP0– = 100 mV Response Time: Mode 1, Vcm ...
Page 77
... Voltage Regulator (REG0) C8051F340/1/2/3/4/5/6/7/8/9 devices include a voltage regulator (REG0). When enabled, the REG0 output appears on the V pin and can be used to power external devices. REG0 can be enabled/disabled by DD software using bit REGEN in register REG0CN. See Table 8.1 for REG0 electrical characteristics. Note that the VBUS signal must be connected to the VBUS pin when using the device in a USB network. ...
Page 78
... C8051F340/1/2/3/4/5/6/7/8/9 VBUS From VBUS REGIN VDD Power Net Figure 8.1. REG0 Configuration: USB Bus-Powered VBUS From VBUS From 5 V REGIN Power Net VDD Power Net Figure 8.2. REG0 Configuration: USB Self-Powered 78 VBUS Sense Voltage Regulator (REG0 Out VBUS Sense Voltage Regulator (REG0 Out Rev ...
Page 79
... Figure 8.3. REG0 Configuration: USB Self-Powered, Regulator Disabled Figure 8.4. REG0 Configuration: No USB Connection ower Net VBUS Sense VBUS VBUS SenseREGIN 3 V Out wer Net 5 V In3 V Out ltag e Reg u lato r ( Device Device Power NetVDD REG0 ) C8051F340/1/2/3/4/5/6/7/8/9 Voltage Regulator (REG0) Rev. 1.1 79 ...
Page 80
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 8.1. REG0CN: Voltage Regulator Control R/W R R/W REGDIS VBSTAT VBPOL Bit7 Bit6 Bit5 Bit7: REGDIS: Voltage Regulator Disable. 0: Voltage Regulator Enabled. 1: Voltage Regulator Disabled. Bit6: VBSTAT: VBUS Signal Status. 0: VBUS signal currently absent (device not attached to USB network). ...
Page 81
... PRGM. ADDRESS REG. CONTROL RESET LOGIC CLOCK STOP POWER CONTROL IDLE Figure 9.1. CIP-51 Block Diagram C8051F340/1/2/3/4/5/6/7/8/9 Section 21), an enhanced full-duplex UART (see description Section 20), 256 bytes of internal RAM, 128 byte (Section 9.2.6), and 25 Port I/O (see description in - Extended Interrupt Handler - Reset Input ...
Page 82
... C8051F340/1/2/3/4/5/6/7/8/9 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for 82 Rev. 1.1 ...
Page 83
... MOVX Instruction and Program Memory In the CIP-51, the MOVX instruction serves three purposes: accessing on-chip XRAM, accessing off-chip data XRAM (only on C8051F340/1/4/5/8 devices), and accessing on-chip program Flash memory. The Flash access feature provides a mechanism for user software to update program code and use the pro- ...
Page 84
... C8051F340/1/2/3/4/5/6/7/8/9 Table 9.1. CIP-51 Instruction Set Summary (Continued) Mnemonic ORL A, #data OR immediate to A ORL direct direct byte ORL direct, #data OR immediate to direct byte XRL A, Rn Exclusive-OR Register to A XRL A, direct Exclusive-OR direct byte to A XRL A, @Ri Exclusive-OR indirect RAM to A XRL A, #data ...
Page 85
... CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ Rn, rel Decrement Register and jump if not zero DJNZ direct, rel Decrement direct byte and jump if not zero NOP No operation C8051F340/1/2/3/4/5/6/7/8/9 Description Boolean Manipulation Program Branching Rev. 1.1 Clock Bytes Cycles ...
Page 86
... C8051F340/1/2/3/4/5/6/7/8/9 Notes on Registers, Operands and Addressing Modes Register R0-R7 of the currently selected register bank. @Ri - Data RAM location addressed indirectly through R0 or R1. rel - 8-bit, signed (two’s complement) offset relative to the first byte of the following instruction. Used by SJMP and all conditional jumps. ...
Page 87
... RESERVED 0xFC00 0xFBFF FLASH (In-System Programmable in 512 Byte Sectors) 0x0000 Figure 9.2. On-Chip Memory Map for 64 kB Devices (C8051F340/2/4/6) C8051F340/1/2/3/4/5/6/7/8/9 DATA MEMORY (RAM) INTERNAL DATA ADDRESS SPACE 0xFF Upper 128 RAM (Indirect Addressing Only) (Direct Addressing Only) 0x80 0x7F ...
Page 88
... Figure 9.3. On-Chip Memory Map for 32 kB Devices (C8051F341/3/5/7/8/9) 9.2.1. Program Memory The CIP-51 core has a 64k-byte program memory space. The C8051F340/1/2/3/4/5/6/7/8/9 implements 64k or 32k bytes of this program memory space as in-system, re-programmable Flash memory. Note that on the C8051F340/2/4/6 (64k version), addresses above 0xFBFF are reserved. ...
Page 89
... Therefore, the first value pushed on the stack is placed at location 0x08, which is also the first register (R0) of register bank 1. Thus, if more than one register bank used, the SP should be initialized to a location in the data memory not being used for data storage. The stack depth can extend up to 256 bytes. C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 89 ...
Page 90
... C8051F340/1/2/3/4/5/6/7/8/9 9.2.6. Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility with the MCS-51™ ...
Page 91
... Internal Oscillator Control OSCLCN 0x86 Internal Low-Frequency Oscillator Control OSCXCN 0xB1 External Oscillator Control P0 0x80 Port 0 Latch P0MDIN 0xF1 Port 0 Input Mode Configuration P0MDOUT 0xA4 Port 0 Output Mode Configuration P0SKIP 0xD4 Port 0 Skip P1 0x90 Port 1 Latch C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 Page 261 152 154 ...
Page 92
... C8051F340/1/2/3/4/5/6/7/8/9 Table 9.3. Special Function Registers (Continued) SFRs are listed in alphabetical order. All undefined SFR locations are reserved. Register Address Description P1MDIN 0xF2 Port 1 Input Mode Configuration P1MDOUT 0xA5 Port 1 Output Mode Configuration P1SKIP 0xD5 Port 1 Skip P2 0xA0 Port 2 Latch P2MDIN ...
Page 93
... USB0XCN 0xD7 USB0 Transceiver Control XBR0 0xE1 Port I/O Crossbar Control 0 XBR1 0xE2 Port I/O Crossbar Control 1 XBR2 0xE3 Port I/O Crossbar Control 2 All Other Addresses Reserved C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 Page 229 228 212 214 216 237 94 248 250 249 250 ...
Page 94
... C8051F340/1/2/3/4/5/6/7/8/9 9.2.7. Register Descriptions Following are descriptions of SFRs related to the operation of the CIP-51 System Controller. Reserved bits should not be set to logic 94 Rev. 1.1 ...
Page 95
... This bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. SFR Definition 9.5. ACC: Accumulator R/W R/W R/W ACC.7 ACC.6 ACC.5 Bit7 Bit6 Bit5 Bits7–0: ACC: Accumulator. This register is the accumulator for arithmetic operations. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W RS1 RS0 OV Bit4 Bit3 Bit2 Address 0 0x00 - 0x07 ...
Page 96
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7– Register. This register serves as a second accumulator for certain arithmetic operations. 9.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting multiple interrupt sources with two priority levels ...
Page 97
... Note that the CPU is stalled during Flash write/erase operations and USB FIFO MOVX accesses (see Section “13.2. Accessing USB FIFO Space” on page interrupts occurring while the CPU is stalled. The latency for these situations will be determined by the standard interrupt service procedure (as described above) and the amount of time the CPU is stalled. C8051F340/1/2/3/4/5/6/7/8/9 IT1 IN1PL /INT1 Interrupt ...
Page 98
... C8051F340/1/2/3/4/5/6/7/8/9 Table 9.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/ 0x0003 INT0) Timer 0 Overflow 0x000B External Interrupt 1 (/ 0x0013 INT1) Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B USB0 0x0043 ADC0 Window 0x004B Compare ADC0 Conversion ...
Page 99
... Disable all Timer 0 interrupt. 1: Enable interrupt requests generated by the TF0 flag. Bit0: EX0: Enable External Interrupt 0. This bit sets the masking of External Interrupt 0. 0: Disable external interrupt 0. 1: Enable interrupt requests generated by the /INT0 input. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W ES0 ET1 ...
Page 100
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.8. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of the SPI0 interrupt. 0: SPI0 interrupt set to low priority level. ...
Page 101
... This bit sets the masking of the USB0 interrupt. 0: Disable all USB0 interrupts. 1: Enable interrupt requests generated by USB0. Bit0: ESMB0: Enable SMBus (SMB0) Interrupt. This bit sets the masking of the SMB0 interrupt. 0: Disable all SMB0 interrupts. 1: Enable interrupt requests generated by SMB0. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W EPCA0 EADC0 EWADC0 EUSB0 ...
Page 102
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0 Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set to low priority level. 1: Timer 3 interrupts set to high priority level. ...
Page 103
... UART1 interrupt set to low priority level. 1: UART1 interrupts set to high priority level. Bit0: PVBUS: VBUS Level Interrupt Priority Control. This bit sets the priority of the VBUS interrupt. 0: VBUS interrupt set to low priority level. 1: VBUS interrupt set to high priority level. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R ...
Page 104
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.13. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to SFR Definition 21.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input is active high. Bits6–4: IN1SL2–0: /INT1 Port Pin Selection Bits These bits select which Port pin is assigned to /INT1. Note that this pin assignment is inde- pendent of the Crossbar ...
Page 105
... If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode. The Missing Clock Detector should be disabled if the CPU put to in STOP mode for longer than the MCD timeout of 100 µsec. C8051F340/1/2/3/4/5/6/7/8/9 Section “14. Oscillators” on page Section “11.6. PCA Watchdog Rev ...
Page 106
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 9.14. PCON: Power Control R/W R/W R/W GF5 GF4 GF3 Bit7 Bit6 Bit5 Bits7–2: GF5–GF0: General Purpose Flags 5–0. These are general purpose flags for use under software control. Bit1: STOP: Stop Mode Select. Setting this bit will place the CIP-51 in Stop mode. This bit will always be read as 0. ...
Page 107
... N : OTES C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 107 ...
Page 108
... C8051F340/1/2/3/4/5/6/7/8/9 108 Rev. 1.1 ...
Page 109
... Prefetch Engine The C8051F340/1/2/3/4/5/6/7/8/9 family of devices incorporate a 2-byte prefetch engine. Because the access time of the FLASH memory is 40 ns, and the minimum instruction time is roughly 20 ns, the prefetch engine is necessary for full-speed code execution. Instructions are read from FLASH memory two bytes at a time by the prefetch engine, and given to the CIP-51 processor core to execute. When running linear code (code without any jumps or branches), the prefetch engine allows instructions to be executed at full speed ...
Page 110
... C8051F340/1/2/3/4/5/6/7/8 OTES 110 Rev. 1.1 ...
Page 111
... Watchdog Timer Mode” on page 284 Program execution begins at location 0x0000. Px.x Px.x System Clock Clock Select Figure 11.1. Reset Sources C8051F340/1/2/3/4/5/6/7/8/9 for information on selecting and configuring details the use of the Watchdog Timer). Missing Clock Detector (one- PCA shot) ...
Page 112
... C8051F340/1/2/3/4/5/6/7/8/9 11.1. Power-On Reset During power-up, the device is held in a reset state and the /RST pin is driven low until Power-On Reset delay (T RST PORDelay typically less than 0.3 ms. Figure 11.2. plots the power-on and V On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other resets) ...
Page 113
... V STAT: V Status This bit indicates the current power supply status ( below the above the Bits5–0: Reserved. Read = Variable. Write = don’t care. C8051F340/1/2/3/4/5/6/7/8/9 Monitor to drop below V DD monitor is enabled and a software reset is DD Monitor Control Bit4 Bit3 Bit2 Monitor cannot generate system resets DD Monitor turn-on time ...
Page 114
... C8051F340/1/2/3/4/5/6/7/8/9 11.3. External Reset The external /RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the /RST pin generates a reset; an external pull-up and/or decoupling of the / RST pin may be necessary to avoid erroneous noise-induced resets. See Table 11.1 for complete /RST pin specifications ...
Page 115
... Section “8. Voltage Regulator (REG0)” on page 77 detection circuit. The USBRSF bit will read ‘1’ following a USB reset. The state of the /RST pin is unaffected by this reset. C8051F340/1/2/3/4/5/6/7/8/9 Section “16. Universal Serial Bus Con- for information on the USB Function Controller. Rev. 1.1 ...
Page 116
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 11.2. RSTSRC: Reset Source R/W R R/W USBRSF FERROR C0RSEF Bit7 Bit6 Bit5 Bit7: USBRSF: USB Reset Flag 0: Read: Last reset was not a USB reset; Write: USB resets disabled. 1: Read: Last reset was a USB reset; Write: USB resets enabled. ...
Page 117
... Delay between release of any Reset Time Delay reset source and code execution at location 0x0000 Minimum /RST Low Time to Generate a System Reset V Monitor Turn-on Time DD V Monitor Supply Current DD C8051F340/1/2/3/4/5/6/7/8/9 Conditions Min = 2 2.40 100 5.0 15 100 Rev. 1.1 ...
Page 118
... C8051F340/1/2/3/4/5/6/7/8 OTES 118 Rev. 1.1 ...
Page 119
... Step 6. Using the MOVX instruction, write a data byte to any location within the 512-byte page to be erased. Step 7. Clear the PSWE bit (register PSCTL). Step 8. Clear the PSEE bit (register PSCTI). C8051F340/1/2/3/4/5/6/7/8/9 Section “23. C2 Interface” Monitor must be enabled before writing and/or DD Rev ...
Page 120
... C8051F340/1/2/3/4/5/6/7/8/9 12.1.3. Flash Write Procedure Bytes in Flash memory can be written one byte at a time groups of two. The FLBWE bit in register PFE0CN (SFR Definition 10.1) controls whether a single byte or a block of two bytes is written to Flash during a write operation. When FLBWE is cleared to ‘0’, the Flash will be written one byte at a time. When FLBWE is set to ‘ ...
Page 121
... Complement: 00000010b Flash pages locked Flash Lock Byte Page) First two pages of Flash: 0x0000 to 0x03FF Addresses locked: Flash Lock Byte Page: (0xFA00 to 0xFBFF for 64k devices; 0x7E00 to 0x7FFF for 32k devices) C8051F340/1/2/3/4/5/6/7/8/9 Conditions Min 65536* 32768 20k 10 40 Rev. 1.1 ...
Page 122
... C8051F340/1/2/3/4/5/6/7/8/9 C8051F340/2/4/6 Reserved Lock Byte FLASH memory organized in 512-byte pages Unlocked FLASH Pages Figure 12.1. Flash Program Memory Map and Security Byte 122 0xFC00 0xFBFF Locked when any 0xFBFE other FLASH pages are locked C8051F341/3/5/7/8/9 0xFA00 Unlocked FLASH Pages Access limit set ...
Page 123
... Unlocking FLASH pages (changing ‘0’s to ‘1’s in the Lock Byte) is not permitted. 7. The Reserved Area cannot be read, written, or erased. Any attempt to access the reserved area, or any other locked page, will result in a FLASH Error device reset. C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 123 ...
Page 124
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 12.1. PSCTL: Program Store R/W Control R/W R/W R Bit7 Bit6 Bit5 Bits7–3: Unused: Read = 00000b. Write = don’t care. Bit2: Reserved. Read = 0b. Must Write = 0b. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows an entire page of Flash program memory to be erased ...
Page 125
... FLRT: FLASH Read Time. This bit should be programmed to the smallest allowed value, according to the system clock speed. 0: SYSCLK <= 25 MHz. 1: SYSCLK <= 48 MHz. Bits3–0: RESERVED. Read = 0000b. Must Write 0000b. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W FLRT Reserved Reserved Reserved Reserved 10000000 ...
Page 126
... C8051F340/1/2/3/4/5/6/7/8 OTES 126 Rev. 1.1 ...
Page 127
... The 1k Bytes of USB FIFO space can also be mapped into XRAM address space for additional general-purpose data storage. Additionally, an External Memory Interface (EMIF) is available on the C8051F340/1/4/5/8 devices, which can be used to access off-chip data memories and memory-mapped devices connected to the GPIO ports. The external memory space may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using the MOVX indirect addressing mode using ...
Page 128
... C8051F340/1/2/3/4/5/6/7/8/9 13.2. Accessing USB FIFO Space The C8051F340/1/2/3/4/5/6/7/8/9 include 1k of RAM which functions as USB FIFO space. Figure 13.1 shows an expanded view of the FIFO space and user XRAM. FIFO space is normally accessed via USB FIFO registers; see Section “16.5. FIFO Management” on page 183 these FIFOs ...
Page 129
... Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases, the output modes of all EMIF pins should be configured for push-pull mode. C8051F340/1/2/3/4/5/6/7/8/9 Section “Figure 15.1. Port I/O Functional Block Diagram (Port 0 Rev. 1.1 Section “ ...
Page 130
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 13.1. EMI0CN: External Memory Interface Control R/W R/W R/W PGSEL7 PGSEL6 PGSEL5 Bit7 Bit6 Bit5 Bits7–0: PGSEL[7:0]: XRAM Page Select Bits. The XRAM Page Select Bits provide the high byte of the 16-bit external data memory address when using an 8-bit MOVX command, effectively selecting a 256-byte page of RAM ...
Page 131
... ALE high and ALE low pulse width = 1 SYSCLK cycle. 01: ALE high and ALE low pulse width = 2 SYSCLK cycles. 10: ALE high and ALE low pulse width = 3 SYSCLK cycles. 11: ALE high and ALE low pulse width = 4 SYSCLK cycles. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W ...
Page 132
... C8051F340/1/2/3/4/5/6/7/8/9 13.5. Multiplexed and Non-multiplexed Selection The External Memory Interface is capable of acting in a Multiplexed mode or a Non-multiplexed mode, depending on the state of the EMD2 (EMI0CF.4) bit. 13.5.1. Multiplexed Configuration In Multiplexed mode, the Data Bus and the lower 8-bits of the Address Bus share the same Port pins: AD[7:0] ...
Page 133
... On-Chip XRAM Off-Chip Memory (No Bank Select) On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM On-Chip XRAM 0x0000 Figure 13.4. EMIF Operating Modes C8051F340/1/2/3/4/5/6/7/8/9 Section “13.7.1. Non-multiplexed Mode” on ADDRESS BUS V DD (Optional) 8 DATA BUS Section “13.7. Timing” on page EMI0CF[3: 0xFFFF ...
Page 134
... C8051F340/1/2/3/4/5/6/7/8/9 13.6.1. Internal XRAM Only When EMI0CF.[3:2] are set to ‘00’, all MOVX instructions will target the internal XRAM space on the device. Memory accesses to addresses beyond the populated space will wrap boundaries (depending on the RAM available on the device example, the addresses 0x1000 and 0x2000 both evaluate to address 0x0000 in on-chip XRAM space. • ...
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... Table 13.1 lists the AC parameters for the External Memory Interface, and Figure 13.5 through Figure 13.10 show the timing diagrams for the different External Mem- ory Interface modes and MOVX operations. C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 135 ...
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... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 13.3. EMI0TC: External Memory Timing Control R/W R/W R/W EAS1 EAS0 EWR3 Bit7 Bit6 Bit5 Bits7–6: EAS1–0: EMIF Address Setup Time Bits. 00: Address setup time = 0 SYSCLK cycles. 01: Address setup time = 1 SYSCLK cycle. 10: Address setup time = 2 SYSCLK cycles. ...
Page 137
... P1.6 ADDR[15:8] P2 ADDR[7:0] P3 DATA[7:0] P4 /RD P1.6 /WR P1.7 Figure 13.5. Non-multiplexed 16-bit MOVX Timing C8051F340/1/2/3/4/5/6/7/8/9 Nonmuxed 16-bit WRITE EMIF ADDRESS (8 MSBs) from DPH EMIF ADDRESS (8 LSBs) from DPL EMIF WRITE DATA T WDS T T ACS ACW Nonmuxed 16-bit READ EMIF ADDRESS (8 MSBs) from DPH ...
Page 138
... C8051F340/1/2/3/4/5/6/7/8/9 13.7.1.2.8-bit MOVX without Bank Select: EMI0CF[4:2] = ‘101’ or ‘111’. Figure 13.6. Non-multiplexed 8-bit MOVX without Bank Select Timing 138 EMIF ADDRESS ( from EMIF ADDRESS (8 LSBs) from EMIF WRITE DATA P1.7 P1.6 Rev. 1.1 P2 P1.7 P1 ...
Page 139
... AD[7: ALEH ALE P1.3 /RD P1.6 /WR P1.7 Figure 13.7. Non-multiplexed 8-bit MOVX with Bank Select Timing C8051F340/1/2/3/4/5/6/7/8/9 Muxed 8-bit WRITE with Bank Select EMIF ADDRESS (8 MSBs) from EMI0CN EMIF WRITE DATA T ALEL T WDS T T ACS ACW Muxed 8-bit READ with Bank Select ...
Page 140
... C8051F340/1/2/3/4/5/6/7/8/9 13.7.2. Multiplexed Mode 13.7.2.1.16-bit MOVX: EMI0CF[4:2] = ‘001’, ‘010’, or ‘011’. ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /WR P1.7 /RD P1.6 ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /RD P1.6 /WR P1.7 Figure 13.8. Multiplexed 16-bit MOVX Timing ...
Page 141
... ADDR[15:8] EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /RD P1.6 /WR P1.7 Figure 13.9. Multiplexed 8-bit MOVX without Bank Select Timing C8051F340/1/2/3/4/5/6/7/8/9 Muxed 8-bit WRITE Without Bank Select P3 EMIF WRITE DATA T ALEL T WDS T T ACS ACW Muxed 8-bit READ Without Bank Select P3 ...
Page 142
... C8051F340/1/2/3/4/5/6/7/8/9 13.7.2.3.8-bit MOVX with Bank Select: EMI0CF[4:2] = ‘010’. ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /WR P1.7 /RD P1.6 ADDR[15:8] P3 EMIF ADDRESS (8 LSBs) from AD[7: ALEH ALE P1.3 /RD P1.6 /WR P1.7 Figure 13.10. Multiplexed 8-bit MOVX with Bank Select Timing 142 ...
Page 143
... Address Latch Enable Low Time ALEL T Write Data Setup Time WDS T Write Data Hold Time WDH T Read Data Setup Time RDS T Read Data Hold Time RDH *Note equal to one period of the device system clock (SYSCLK). SYSCLK C8051F340/1/2/3/4/5/6/7/8/9 Min SYSCLK SYSCLK SYSCLK ...
Page 144
... C8051F340/1/2/3/4/5/6/7/8 OTES 144 Rev. 1.1 ...
Page 145
... Oscillators C8051F340/1/2/3/4/5/6/7/8/9 devices include a programmable internal high-frequency oscillator, a pro- grammable internal low-frequency oscillator (C8051F340/1/2/3/4/5/8/9), an external oscillator drive circuit, and a 4x Clock Multiplier. The internal high-frequency and low-frequency oscillators can be enabled/dis- abled and adjusted using the special function registers, as shown in Figure 14.1. The system clock (SYS- CLK) can be derived from either of the internal oscillators, the external oscillator circuit, or the 4x Clock Multiplier divided by 2 ...
Page 146
... C8051F340/1/2/3/4/5/6/7/8/9 14.1. Programmable Internal High-Frequency (H-F) Oscillator All C8051F340/1/2/3/4/5/6/7/8/9 devices include a programmable internal oscillator that defaults as the system clock after a system reset. The internal oscillator period can be programmed via the OSCICL regis- ter shown in SFR Definition 14.2. The OSCICL register is factory calibrated to obtain a 12 MHz internal oscillator frequency ...
Page 147
... USB Clock Configuration” on page 182 14.2. Programmable Internal Low-Frequency (L-F) Oscillator The C8051F340/1/2/3/4/5/8/9 devices include a programmable internal oscillator which operates at a nom- inal frequency of 80 kHz. The low-frequency oscillator circuit includes a divider that can be changed to divide the clock using the OSCLD bits in the OSCLCN register (see SFR Definition 14.3). ...
Page 148
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 14.3. OSCLCN: Internal L-F Oscillator Control R/W R R/W OSCLEN OSCLRDY OSCLF3 Bit7 Bit6 Bit5 Bit7: OSCLEN: Internal L-F Oscillator Enable. 0: Internal L-F Oscillator Disabled. 1: Internal L-F Oscillator Enabled. Bit6: OSCLRDY: Internal L-F Oscillator Ready Flag. 0: Internal L-F Oscillator frequency not stabilized. ...
Page 149
... Important Note on External Oscillator Usage: Port pins must be configured when using the external oscillator circuit. When the external oscillator drive circuit is enabled in crystal/resonator mode, Port pins P0.6 and P0.7 (C8051F340/1/4/5/8) or P0.2 and P0.3 (C8051F342/3/6/7/9) are used as XTAL1 and XTAL2 respectively. When the external oscillator drive circuit is enabled in capacitor, RC, or CMOS clock mode, Port pin P0.7 (C8051F340/1/4/5/8) or P0.3 (C8051F342/3/6/7/9) is used as XTAL2. The Port I/O Crossbar should be configured to skip the Port pins used by the oscillator circuit ...
Page 150
... C8051F340/1/2/3/4/5/6/7/8/9 14.3.3. External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 14.1, Option 2. The capacitor should be no greater than 100 pF; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the PCB layout. To deter- mine the required External Oscillator Frequency Control value (XFCN) in the OSCXCN Register, first select the RC network value to produce the desired frequency of oscillation ...
Page 151
... R = Pull-up resistor value in k Ω C MODE (Circuit from Figure 14.1, Option 3; XOSCMD = 10x) Choose K Factor (KF) for the oscillation frequency desired where frequency of clock in MHz C = capacitor value the XTAL2 pin Power Supply on MCU in volts DD C8051F340/1/2/3/4/5/6/7/8/9 R/W R R/W R/W - XFCN2 XFCN1 Bit4 Bit3 Bit2 ...
Page 152
... USB communication (see Section “16.4. USB Clock Configuration” on page 182 the Multiplier output can also be used as the system clock. C8051F340/1/2/3 devices can use the 48 MHz Clock Multiplier output as system clock. See Table 3.1, “Global DC Electrical Characteristics,” on page 38 for system clock frequency specifications. See source selection ...
Page 153
... The system clock may be switched on-the-fly between the internal oscillator, external oscillator, and 4x Clock Multiplier so long as the selected oscillator is enabled and has settled. C8051F340/ 1/2/3 devices can use the 48 MHz Clock Multiplier output as system clock. See Table 3.1, “Global DC Elec- trical Characteristics,” ...
Page 154
... MHz ( MHz), the FLRT bit (FLSCL.4) should be set to ‘1’. See “10. Prefetch Engine” on page 109 CLKSL 000 001 010 011* 100 101-111 *Note: This option is only available on 48 MHz devices (C8051F340/1/2/3/4). 154 Register Bit Settings USBCLK = 101b XOSCMD = 110b XFCN = 111b R/W R/W R/W ...
Page 155
... Internal Low-Frequency Oscillator (Using Factory-Calibrated Settings) Oscillator Frequency OSCLD = 11b Oscillator Supply Current 24 ºC, V (from V ) OSCLCN External USB Clock Requirements Full Speed Mode USB Clock Frequency* Low Speed Mode *Note: Applies only to external oscillator sources. C8051F340/1/2/3/4/5/6/7/8/9 Conditions Min 11.82 12. — 3 — 47.88 5.91 Rev ...
Page 156
... C8051F340/1/2/3/4/5/6/7/8 OTES 156 Rev. 1.1 ...
Page 157
... Port Input/Output Digital and analog resources are available through 40 I/O pins (C8051F340/1/4/5/ I/O pins (C8051F342/3/6/7/9). Port pins are organized as shown in Figure 15.1. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P3.7 can be assigned to one of the internal digital resources as shown in Figure 15.3. The designer has complete control over which functions are assigned, limited only by the number of physical I/O pins ...
Page 158
... C8051F340/1/2/3/4/5/6/7/8/9 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT Figure 15.2. Port I/O Cell Block Diagram 158 VDD GND Analog Select Rev. 1.1 VDD (WEAK) PORT PAD ...
Page 159
... ECI T0 T1 TX1** RX1** Port pin potentially available to peripheral SF Signals Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must be manually configured to skip their corresponding port pins. Figure 15.3. Peripheral Availability on Port I/O Pins C8051F340/1/2/3/4/5/6/7/8 ...
Page 160
... C8051F340/1/2/3/4/5/6/7/8 Signals (32-pin Package) SF Signals (48-pin Package) PIN I TX0 RX0 SCK MISO MOSI NSS* *NSS is only pinned out in 4-wire SPI mode SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI T0 T1 TX1** RX1 P0SKIP[0:7] Port pin assigned to peripheral by the Crossbar SF Signals Special Function Signals are not assigned by the Crossbar ...
Page 161
... Important Note: The SPI can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be routed to a Port pin. 15.2. Port I/O Initialization Port I/O initialization consists of the following steps: C8051F340/1/2/3/4/5/6/7/8 ...
Page 162
... C8051F340/1/2/3/4/5/6/7/8/9 Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or push-pull) for all Port pins, using the Port Output Mode register (PnMDOUT). Step 3. Select any pins to be skipped by the I/O Crossbar using the Port Skip registers (PnSKIP). ...
Page 163
... SPI0E: SPI I/O Enable 0: SPI I/O unavailable at Port pins. 1: SPI I/O routed to Port pins. Bit0: URT0E: UART0 I/O Output Enable 0: UART0 I/O unavailable at Port pins. 1: UART0 TX0, RX0 routed to Port pins P0.4 and P0.5. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W CP0E SYSCKE ...
Page 164
... SFR Definition 15.3. XBR2: Port I/O Crossbar Register 2 R/W R/W R/W Bit7 Bit6 Bit5 Bits7–1: RESERVED: Always write to 0000000b Bit0: URT1E: UART1 I/O Output Enable (C8051F340/1/4/5/8 Only) 0: UART1 I/O unavailable at Port pins. 1: UART1 TX1, RX1 routed to Port pins. 164 R/W R/W R/W R/W T0E ...
Page 165
... I/O. Ports 3-0 are accessed through corresponding special function registers (SFRs) that are both byte addressable and bit addressable. Port 4 (C8051F340/1/4/5/8 only) uses an SFR which is byte-addressable. When writing to a Port, the value written to the SFR is latched to maintain the output data value at each pin ...
Page 166
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.6. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. (Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT) ...
Page 167
... R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Output Configuration Bits for P1.7–P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n Output is push-pull. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W P1.4 P1.3 P1.2 P1.1 Bit4 ...
Page 168
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.11. P1SKIP: Port1 Skip R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: P1SKIP[7:0]: Port1 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar ...
Page 169
... These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P2.n pin is not skipped by the Crossbar. 1: Corresponding P2.n pin is skipped by the Crossbar. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W ...
Page 170
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.16. P3: Port3 Latch R/W R/W R/W P3.7 P3.6 P3.5 Bit7 Bit6 Bit5 Bits7–0: P3.[7:0] Write - Output appears on I/O pins. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P3MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input ...
Page 171
... Logic High Output (high impedance if corresponding P4MDOUT.n bit = 0). Read - Always reads ‘0’ if selected as analog input in register P4MDIN. Directly reads Port pin when configured as digital input. 0: P4.n pin is logic low. 1: P4.n pin is logic high. Note only available on 48-pin devices. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W Bit4 ...
Page 172
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 15.21. P4MDIN: Port4 Input Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7–0: Analog Input Configuration Bits for P4.7–P4.0 (respectively). Port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: Corresponding P4.n pin is configured as an analog input. ...
Page 173
... Output High Voltage –10 mA, Port I/O push-pull 8 µA Output Low Voltage Input High Voltage Input Low Voltage Weak Pull-up Off Input Leakage Current Weak Pull-up On, V C8051F340/1/2/3/4/5/6/7/8/9 Conditions Min V – 0 – 0 Rev. 1.1 Typ Max Units V V – 0.8 DD ...
Page 174
... C8051F340/1/2/3/4/5/6/7/8/9 174 Rev. 1.1 ...
Page 175
... Universal Serial Bus Controller (USB0) C8051F340/1/2/3/4/5/6/7/8/9 devices include a complete Full/Low Speed USB function for USB peripheral implementations*. The USB Function Controller (USB0) consists of a Serial Interface Engine (SIE), USB Transceiver (including matching resistors and configurable pull-up resistors), 1k FIFO block, and clock recovery mechanism for crystal-less operation ...
Page 176
... C8051F340/1/2/3/4/5/6/7/8/9 16.1. Endpoint Addressing A total of eight endpoint pipes are available. The control endpoint (Endpoint0) always functions as a bi-directional IN/OUT endpoint. The other endpoints are implemented as three pairs of IN/OUT endpoint pipes: Table 16.1. Endpoint Addressing Scheme Endpoint Associated Pipes Endpoint0 Endpoint1 Endpoint2 Endpoint3 16 ...
Page 177
... This bit indicates the current logic level of the D+ pin signal currently at logic signal currently at logic 1. Bit0: Dn: D- Signal Status This bit indicates the current logic level of the D– pin. 0: D– signal currently at logic 0. 1: D– signal currently at logic 1. C8051F340/1/2/3/4/5/6/7/8/9 R/W R Bit4 Bit3 ...
Page 178
... C8051F340/1/2/3/4/5/6/7/8/9 16.3. USB Register Access The USB0 controller registers listed in Table 16.2 are accessed through two SFRs: USB0 Address (USB0ADR) and USB0 Data (USB0DAT). The USB0ADR register selects which USB register is targeted by reads/writes of the USB0DAT register. See Figure 16.2. Endpoint control/status registers are accessed by first writing the USB register INDEX with the target end- point number. Once the target endpoint number is written to the INDEX register, the control/status registers associated with the target endpoint may be accessed. See the “ ...
Page 179
... Bits5–0: USBADDR: USB0 Indirect Register Address These bits hold a 6-bit address used to indirectly access the USB0 core registers. Table 16.2 lists the USB0 core registers and their indirect addresses. Reads and writes to USB0DAT will target the register indicated by the USBADDR bits. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W ...
Page 180
... C8051F340/1/2/3/4/5/6/7/8/9 SFR Definition 16.3. USB0DAT: USB0 Data R/W R/W R/W Bit7 Bit6 Bit5 This SFR is used to indirectly read and write USB0 registers. Write Procedure: 1. Poll for BUSY (USB 0ADR.7) => ‘0’. 2. Load the target USB0 register address into the USBADDR bits in register USB0ADR. ...
Page 181
... These bits select which endpoint is targeted when indexed USB0 registers are accessed. INDEX Target Endpoint 0x0 0x1 0x2 0x3 0x4–0xF C8051F340/1/2/3/4/5/6/7/8/9 Description Interrupt Registers Endpoint0 and Endpoints1-3 IN Interrupt Flags Endpoints1-3 OUT Interrupt Flags Common USB Interrupt Flags Endpoint0 and Endpoints1-3 IN Interrupt Enables Endpoints1-3 OUT Interrupt Enables ...
Page 182
... C8051F340/1/2/3/4/5/6/7/8/9 16.4. USB Clock Configuration USB0 is capable of communication as a Full or Low Speed USB function. Communication speed is selected via the SPEED bit in SFR USB0XCN. When operating as a Low Speed function, the USB0 clock must be 6 MHz. When operating as a Full Speed function, the USB0 clock must be 48 MHz. Clock options are described in Section “ ...
Page 183
... IN or OUT FIFO. In this case only one direction of the endpoint IN/OUT pair may be used at a time. The endpoint direction (IN/OUT) is determined by the DIRSEL bit in the corresponding endpoint’s EINCSRH register (see SFR Definition 16.20). C8051F340/1/2/3/4/5/6/7/8/9 Configurable as IN, OUT, or both (Split ...
Page 184
... C8051F340/1/2/3/4/5/6/7/8/9 16.5.2. FIFO Double Buffering FIFO slots for Endpoints1-3 can be configured for double-buffered mode. In this mode, the maximum packet size is halved and the FIFO may contain two packets at a time. This mode is available for Endpoints1-3. When an endpoint is configured for Split Mode, double buffering may be enabled for the IN Endpoint and/or the OUT endpoint ...
Page 185
... Suspend Mode: With Suspend Detection enabled (SUSEN = ‘1’), USB0 will enter Suspend Mode when Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = ‘1’). The Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as disabling appropriate peripherals and/or configuring clock sources for low power modes. See C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W ...
Page 186
... C8051F340/1/2/3/4/5/6/7/8/9 “14. Oscillators” on page 145 for more details on internal oscillator configuration, including the Suspend mode feature of the internal oscillator. USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener- ated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscil- lator will exit Suspend mode upon any of the above listed events ...
Page 187
... USB0 not in suspend mode. 1: USB0 in suspend mode. Bit0: SUSEN: Suspend Detection Enable 0: Suspend detection disabled. USB0 will ignore suspend signaling on the bus. 1: Suspend detection enabled. USB0 will enter suspend mode if it detects suspend signaling on the bus. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R USBRST RESUME SUSMD ...
Page 188
... C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.9. FRAMEL: USB0 Frame Number Low Bit7 Bit6 Bit5 Bits7-0: Frame Number Low This register contains bits7-0 of the last received frame number. USB Register Definition 16.10. FRAMEH: USB0 Frame Number High Bit7 Bit6 Bit5 Bits7-3: Unused. Read = 0. Write = don’t care. ...
Page 189
... OUT Endpoint 2 interrupt inactive. 1: OUT Endpoint 2 interrupt active. Bit1: OUT1: OUT Endpoint 1 Interrupt-pending Flag This bit is cleared when software reads the OUT1INT register. 0: OUT Endpoint 1 interrupt inactive. 1: OUT Endpoint 1 interrupt active. Bit0: Unused. Read = 0; Write = don’t care. C8051F340/1/2/3/4/5/6/7/8 IN3 IN2 IN1 ...
Page 190
... C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.13. CMINT: USB0 Common Interrupt Bit7 Bit6 Bit5 Bits7–4: Unused. Read = 0000b; Write = don’t care. Bit3: SOF: Start of Frame Interrupt Set by hardware when a SOF token is received. This interrupt event is synthesized by hard- ware: an interrupt will be generated when hardware expects to receive a SOF event, even if the actual SOF signal is missed or corrupted ...
Page 191
... OUT2E: OUT Endpoint 2 Interrupt Enable 0: OUT Endpoint 2 interrupt disabled. 1: OUT Endpoint 2 interrupt enabled. Bit1: OUT1E: OUT Endpoint 1 Interrupt Enable 0: OUT Endpoint 1 interrupt disabled. 1: OUT Endpoint 1 interrupt enabled. Bit0: Unused. Read = 0; Write = don’t’ care. C8051F340/1/2/3/4/5/6/7/8/9 R/W R/W R/W R/W - IN3E IN2E IN1E ...
Page 192
... C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.16. CMIE: USB0 Common Interrupt Enable 16.9. The Serial Interface Engine The Serial Interface Engine (SIE) performs all low level USB protocol tasks, interrupting the processor when data has successfully been transmitted or received. When receiving data, the SIE will interrupt the processor when a complete data packet has been received ...
Page 193
... Firmware sends a packet less than the maximum Endpoint0 packet size. 3. Firmware sends a zero-length packet. Firmware should set the DATAEND bit (E0CSR.3) to ‘1’ when performing (2) and (3) above. The SIE will transmit a NAK in response token if there is no packet ready in the IN FIFO (INPRDY = ‘0’). C8051F340/1/2/3/4/5/6/7/8/9 Rev. 1.1 193 ...
Page 194
... C8051F340/1/2/3/4/5/6/7/8/9 16.10.3.Endpoint0 OUT Transactions When a SETUP request is received that requires the host to transmit data to USB0, one or more OUT requests will be sent by the host. When an OUT packet is successfully received by USB0, hardware will set the OPRDY bit (E0CSR.0) to ‘1’ and generate an Endpoint0 interrupt. Following this interrupt, firmware should unload the OUT packet from the Endpoint0 FIFO and set the SOPRDY bit (E0CSR.6) to ‘ ...
Page 195
... The packet is overwritten by an incoming OUT packet. Bit0: OPRDY: OUT Packet Ready Hardware sets this read-only bit and generates an interrupt when a data packet has been received. This bit is cleared only when software writes ‘1’ to the SOPRDY bit. C8051F340/1/2/3/4/5/6/7/8/9 R R/W R/W R/W ...
Page 196
... C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.18. E0CNT: USB0 Endpoint 0 Data Count Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bits6–0: E0CNT: Endpoint 0 Data Count This 7-bit number indicates the number of received data bytes in the Endpoint 0 FIFO. This number is only valid while bit OPRDY is a ‘1’. ...
Page 197
... FIFO. The ISO Update feature ensures that any data packet written to the endpoint FIFO will not be transmitted during the current frame; the packet will only be sent after a SOF signal has been received. C8051F340/1/2/3/4/5/6/7/8/9 ) can be useful in starting a double buffered ISO IN endpoint. If Rev. 1.1 ...
Page 198
... C8051F340/1/2/3/4/5/6/7/8/9 USB Register Definition 16.19. EINCSRL: USB0 IN Endpoint Control Low Byte R W R/W - CLRDT STSTL Bit7 Bit6 Bit5 Bit7: Unused. Read = 0; Write = don’t care. Bit6: CLRDT: Clear Data Toggle. Write: Software should write ‘1’ to this bit to reset the IN Endpoint data toggle to ‘0’. ...
Page 199
... OUT token and data packet. The number of bytes in the current OUT data packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL reg- isters. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset the OPRDY bit to ‘0’. C8051F340/1/2/3/4/5/6/7/8/9 R R/W R/W ...
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... C8051F340/1/2/3/4/5/6/7/8/9 A Bulk or Interrupt pipe can be shut down (or Halted) by writing ‘1’ to the SDSTL bit (EOUTCSRL.5). While SDSTL = ‘1’, hardware will respond to all OUT requests with a STALL condition. Each time hardware gen- erates a STALL condition, an interrupt will be generated and the STSTL bit (EOUTCSRL.6) set to ‘1’. The STSTL bit must be reset to ‘ ...