C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 167

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

C8051F040/1/2/3/4/5/6/7
lup and/or decoupling of the /RST pin to avoid erroneous noise-induced resets. The MCU will remain in
reset until at least 12 clock cycles after the active-low /RST signal is removed. The PINRSF flag (RST-
SRC.0) is set on exit from an external reset.
13.4. Missing Clock Detector Reset
The Missing Clock Detector is essentially a one-shot circuit that is triggered by the MCU system clock. If
the system clock goes away for more than 100 µs, the one-shot will time out and generate a reset. After a
Missing Clock Detector reset, the MCDRSF flag (RSTSRC.2) will be set, signifying the MCD as the reset
source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by this reset. Setting the
MCDRSF bit, RSTSRC.2 (see Section
“14.
Oscillators” on page 173) enables the Missing Clock Detector.
13.5. Comparator0 Reset
Comparator0 can be configured as a reset input by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled using CPT0CN.7 (see Section
“11.
Comparators” on page 121) prior to
writing to C0RSEF to prevent any turn-on chatter on the output from generating an unwanted reset. The
Comparator0 reset is active-low: if the non-inverting input voltage (CP0+ pin) is less than the inverting
input voltage (CP0- pin), the MCU is put into the reset state. After a Comparator0 Reset, the C0RSEF flag
(RSTSRC.5) will read ‘1’ signifying Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state
of the /RST pin is unaffected by this reset.
13.6. External CNVSTR0 Pin Reset
The external CNVSTR0 signal can be configured as a reset input by writing a ‘1’ to the CNVRSEF flag
(RSTSRC.6). The CNVSTR0 signal can appear on any of the P0, P1, P2 or P3 I/O pins as described in
Section
“17.1. Ports 0 through 3 and the Priority Crossbar
Decoder” on page 204. Note that the Cross-
bar must be configured for the CNVSTR0 signal to be routed to the appropriate Port I/O. The Crossbar
should be configured and enabled before the CNVRSEF is set. When configured as a reset, CNVSTR0 is
active-low and level sensitive. After a CNVSTR0 reset, the CNVRSEF flag (RSTSRC.6) will read ‘1’ signi-
fying CNVSTR0 as the reset source; otherwise, this bit reads ‘0’. The state of the /RST pin is unaffected by
this reset.
13.7. Watchdog Timer Reset
The MCU includes a programmable Watchdog Timer (WDT) running off the system clock. A WDT overflow
will force the MCU into the reset state. To prevent the reset, the WDT must be restarted by application soft-
ware before overflow. If the system experiences a software or hardware malfunction preventing the soft-
ware from restarting the WDT, the WDT will overflow and cause a reset. This should prevent the system
from running out of control.
Following a reset the WDT is automatically enabled and running with the default maximum time interval. If
desired the WDT can be disabled by system software or locked on to prevent accidental disabling. Once
locked, the WDT cannot be disabled until the next system reset. The state of the /RST pin is unaffected by
this reset.
The WDT consists of a 21-bit timer running from the programmed system clock. The timer measures the
period between specific writes to its control register. If this period exceeds the programmed limit, a WDT
reset is generated. The WDT can be enabled and disabled as needed in software, or can be permanently
enabled if desired. Watchdog features are controlled via the Watchdog Timer Control Register (WDTCN)
shown in SFR Definition 13.1.
Rev. 1.5
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