C8051F346-GQ Silicon Laboratories Inc, C8051F346-GQ Datasheet - Page 90
![IC 8051 MCU FLASH 64K 32LQFP](/photos/12/18/121867/c8051f346-gq_sml.jpg)
C8051F346-GQ
Manufacturer Part Number
C8051F346-GQ
Description
IC 8051 MCU FLASH 64K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets
1.C8051F349-GQ.pdf
(276 pages)
2.C8051F346-GQ.pdf
(1 pages)
3.C8051F347-GQ.pdf
(296 pages)
Specifications of C8051F346-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
5.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
25
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1304
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C8051F340/1/2/3/4/5/6/7/8/9
9.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 9.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, SCON0, IE, etc.) are
bit-addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the datasheet, as indicated in Table 9.3,
for a detailed description of each register.
90
D8 PCA0CN
D0
C8 TMR2CN
C0 SMB0CN
F8
F0
E8 ADC0CN PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 PCA0CPL3 PCA0CPH3
E0
B8
B0
A8
A0
98
90
88
80
(bit addressable)
SPI0CN
SCON0
TCON
PSW
ACC
0(8)
P3
P2
P1
P0
IP
IE
B
Table 9.2. Special Function Register (SFR) Memory Map
PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 PCA0CPM3 PCA0CPM4
REG0CN
OSCXCN
SPI0CFG
TMR3CN
SMB0CF
CLKMUL
REF0CN
CLKSEL
P0MDIN
SBUF0
PCA0L
TMOD
XBR0
1(9)
SP
SMB0DAT ADC0GTL ADC0GTH
TMR2RLL TMR2RLH
TMR3RLL TMR3RLH
SPI0CKR
CPT1CN
OSCICN
P1MDIN
EMI0CN
SCON1
AMX0N
PCA0H
XBR1
DPL
2(A)
TL0
PCA0CPL0 PCA0CPH0 PCA0CPL4 PCA0CPH4 VDM0CN
SPI0DAT
CPT0CN
P2MDIN
OSCICL
AMX0P
SBUF1
XBR2
DPH
3(B)
TL1
-
Rev. 1.1
P0MDOUT P1MDOUT P2MDOUT P3MDOUT
SBCON1
CPT1MD
ADC0CF
P3MDIN
SBRLL1
EMI0TC
P0SKIP
IT01CF
TMR3L
TMR2L
4(C)
TH0
ADC0LTL
CPT0MD
SBRLH1
P4MDIN
EMI0CF
SMOD1
P1SKIP
TMR2H
TMR3H
ADC0L
5(D)
TH1
-
P4MDOUT
USB0ADR
ADC0LTH
OSCLCN
CPT1MX
CKCON
P2SKIP
ADC0H
FLSCL
EIP1
EIE1
6(E)
-
USB0XCN
USB0DAT
RSTSRC
CPT0MX
PFE0CN
P3SKIP
FLKEY
PSCTL
PCON
EIP2
EIE2
7(F)
P4
-
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