EE87C51RB1 Intel, EE87C51RB1 Datasheet - Page 6

• Manufacturer Part Number: EE87C51RB1
• Description: IC MCU 8BIT 5V 16MHZ OTP 44PLCC
• Manufacturer: Intel
• Series: 87Cr

Specifications of EE87C51RB1

• Core Processor: MCS 51
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 864637

8XC51RA RB RC
Mode will be exited if the chip is reset or if an en-
abled interrupt occurs
POWER DOWN MODE
To save even more power a Power Down mode can
be invoked by software In this mode the oscillator
is stopped and the instruction that invoked Power
Down is the last instruction executed The on-chip
RAM and Special Function Registers retain their val-
ues until the Power Down mode is terminated
On the 8XC51RX either a hardware reset or an ex-
ternal interrupt can cause an exit from Power Down
Reset redefines all the SFRs but does not change
the on-chip RAM An external interrupt allows both
the SFRs and on-chip RAM to retain their values
To properly terminate Power Down the reset or ex-
ternal interrupt should not be executed before V
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms)
With an external interrupt INT0 and INT1 must be
enabled and configured as level-sensitive Holding
the pin low restarts the oscillator but bringing the pin
back high completes the exit Once the interrupt is
serviced the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down
DEDICATED HARDWARE WATCHDOG
TIMER (One-Time Enabled with
Reset-Out)
The 8XC51RX contains a dedicated WatchDog Tim-
er (WDT) to allow recovery from software or hard-
NOTE
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I (Order No 270645) and Application Note AP-252 (Embedded Applications Handbook Order No
270648) ‘‘Designing with the 80C51BH ’’
6
Idle
Idle
Power Down
Power Down
Mode
Table 2 Status of the External Pins during Idle and Power Down
Program
Memory
External
External
Internal
Internal
ALE
1
1
0
0
PSEN
CC
1
1
0
0
is
ware upset WDT is disabled upon power-up To en-
able the WDT user must write 1EH and E1H in se-
quence to WDTRST Special Function Register
Once the WDT is enabled the 14-bit counter will
increment every machine cycle While the oscillator
is running the WDT will be incrementing and cannot
be disabled The counter is reset by writing 1EH and
E1H in sequence to the WDTRST If the counter is
not reset before it reaches 3FFFH (16383D) the
chip will be forced into reset sequence and the WDT
will be disabled as upon power-up During this reset
the chip will drive an output Reset-High pulse for the
duration of 96 x T
of the Reset-High pulse works out to 6 00
16 MHz
While in the Idle mode the WDT continues to count
If the user does not wish to exit the Idle mode with a
reset then the processor must periodically ‘‘woken
up’’ to service the WDT In Power Down mode the
WDT stops counting and holds its current value
DESIGN CONSIDERATION
PORT0
Float
Float
Data
Data
The window on the D87C51RX must be covered
by an opaque label Otherwise the DC and AC
characteristics may not be met and the device
may be functionally impaired
When the idle mode is terminated by a hardware
reset the device normally resumes program exe-
cution from where it left off up to two machine
cycles before the internal reset algorithm takes
control On-chip hardware inhibits access to inter-
nal RAM in this event but access to the port pins
is not inhibited To eliminate the possibility of an
unexpected write when Idle is terminated by re-
set the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory
PORT1
Data
Data
Data
Data
OSC
at the RST pin The duration
Address
PORT2
Data
Data
Data
PORT3
Data
Data
Data
Data
s