C8051F361-GQ Silicon Laboratories Inc, C8051F361-GQ Datasheet - Page 130

• Manufacturer Part Number: C8051F361-GQ
• Description: IC 8051 MCU 32K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F361-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 21x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 100 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1408

C8051F360/1/2/3/4/5/6/7/8/9
12.2. Power-Fail Reset/V
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 12.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
Monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any
other reset source. For example, if the V
Monitor will still be disabled after the reset. To protect the integrity of Flash contents, the V
must be enabled and selected as a reset source if software contains routines which erase or write
Flash memory. If the V
will cause a Flash Error device reset.
The V
as a reset source before it is enabled and stabilized may cause a system reset. The procedure for config-
uring the V
See Table 12.1 for complete electrical characteristics of the V
Note: Software should take care not to inadvertently disable the V
when writing to RSTSRC to enable other reset sources or to trigger a software reset. All writes to
RSTSRC should explicitly set PORSF to '1' to keep the V
130
DD
Step 1. Enable the V
Step 2. Wait for the V
Step 3. Select the V
Monitor must be enabled before it is selected as a reset source. Selecting the V
DD
Monitor as a reset source is shown below:
Note: This delay should be omitted if software contains routines which erase or
write Flash memory.
RST
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
Monitor is not enabled, any erase or write performed on Flash memory
DD
DD
DD
Monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
DD
Monitor (VDMEN bit in VDM0CN = ‘1’).
Monitor to stabilize (approximately 5 µs).
Monitor
DD
Monitor is disabled and a software reset is performed, the V
Rev. 1.0
DD
DD
DD
Monitor enabled as a reset source.
Monitor.
to drop below V
DD
Monitor as a reset source
RST
, the power supply
DD
dropped below
DD
DD
DD
Monitor
Monitor
returns
DD
DD