MC9S08DZ60ACLF Freescale Semiconductor, MC9S08DZ60ACLF Datasheet - Page 184
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MC9S08DZ60ACLF
Manufacturer Part Number
MC9S08DZ60ACLF
Description
IC MCU 60K FLASH 4K RAM 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheets
1.DEMO9S08DZ60.pdf
(416 pages)
2.EVB9S08DZ60.pdf
(4 pages)
3.MC9S08DZ48AMLF.pdf
(458 pages)
Specifications of MC9S08DZ60ACLF
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Processor Series
S08DZ
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
CAN, I2C, SCI, SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
2
Operating Supply Voltage
5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08DZ60
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 24 Channel
For Use With
DEMO9S08DZ60 - BOARD DEMOEVB9S08DZ60 - BOARD EVAL FOR 9S08DZ60
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S08DZ60ACLF
Manufacturer:
FREESCAL
Quantity:
1 250
Company:
Part Number:
MC9S08DZ60ACLF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
10.3.8
184
The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is
ADICLK
MODE
Field
3:2
1:0
Pin Control 1 Register (APCTL1)
Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See
Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
10-9.
Table 10-6. ADCCFG Register Field Descriptions (continued)
ADICLK
MODE
ADIV
00
01
10
11
00
01
10
11
00
01
10
11
8-bit conversion (N=8)
12-bit conversion (N=12)
10-bit conversion (N=10)
Reserved
Bus clock
Bus clock divided by 2
Alternate clock (ALTCLK)
Asynchronous clock (ADACK)
MC9S08DZ60 Series Data Sheet, Rev. 4
Table 10-7. Clock Divide Select
Table 10-8. Conversion Modes
Table 10-9. Input Clock Select
Divide Ratio
1
2
4
8
Selected Clock Source
Mode Description
Description
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
Freescale Semiconductor
Table
10-8.
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