C8051F347-GQ Silicon Laboratories Inc, C8051F347-GQ Datasheet - Page 199
![IC 8051 MCU FLASH 32K 32LQFP](/photos/12/18/121823/c8051f347-gq_sml.jpg)
C8051F347-GQ
Manufacturer Part Number
C8051F347-GQ
Description
IC 8051 MCU FLASH 32K 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheets
1.C8051F349-GQ.pdf
(276 pages)
2.C8051F347-GQ.pdf
(1 pages)
3.C8051F347-GQ.pdf
(296 pages)
Specifications of C8051F347-GQ
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 21x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
3.25 KB
Interface Type
I2C/SMBus/SPI/UART/USB
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
17-ch x 10-bit
No. Of I/o's
25
Ram Memory Size
2304Byte
Cpu Speed
25MHz
No. Of Timers
4
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X770-1006 - ISP 4PORT FOR SILABS C8051F MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1305
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F347-GQ
Manufacturer:
LELON
Quantity:
30 000
Company:
Part Number:
C8051F347-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F347-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 199 of 296
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16.13. Controlling Endpoints1-3 OUT
Endpoints1-3 OUT are managed via USB registers EOUTCSRL and EOUTCSRH. All OUT endpoints can
be used for Interrupt, Bulk, or Isochronous transfers. Isochronous (ISO) mode is enabled by writing ‘1’ to
the ISO bit in register EOUTCSRH. Bulk and Interrupt transfers are handled identically by hardware.
An Endpoint1-3 OUT interrupt may be generated by the following:
16.13.1.Endpoints1-3 OUT Interrupt or Bulk Mode
When the ISO bit (EOUTCSRH.6) = ‘0’ the target endpoint operates in Bulk or Interrupt mode. Once an
endpoint has been configured to operate in Bulk/Interrupt OUT mode (typically following an Endpoint0
SET_INTERFACE command), hardware will set the OPRDY bit (EOUTCSRL.0) to ‘1’ and generate an
interrupt upon reception of an OUT token and data packet. The number of bytes in the current OUT data
packet (the packet ready to be unloaded from the FIFO) is given in the EOUTCNTH and EOUTCNTL reg-
isters. In response to this interrupt, firmware should unload the data packet from the OUT FIFO and reset
the OPRDY bit to ‘0’.
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bits1–0: Unused. Read = 00b; Write = don’t care.
USB Register Definition 16.20. EINCSRH: USB0 IN Endpoint Control High Byte
DBIEN
R/W
Bit7
1. Hardware sets the OPRDY bit (EINCSRL.0) to ‘1’.
2. Hardware generates a STALL condition.
DBIEN: IN Endpoint Double-buffer Enable.
0: Double-buffering disabled for the selected IN endpoint.
1: Double-buffering enabled for the selected IN endpoint.
ISO: Isochronous Transfer Enable.
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
DIRSEL: Endpoint Direction Select.
This bit is valid only when the selected FIFO is not split (SPLIT = ‘0’).
0: Endpoint direction selected as OUT.
1: Endpoint direction selected as IN.
Unused. Read = ‘0’. Write = don’t care.
FCDT: Force Data Toggle.
0: Endpoint data toggle switches only when an ACK is received following a data packet
transmission.
1: Endpoint data toggle forced to switch after every data packet is transmitted, regardless of
ACK reception.
SPLIT: FIFO Split Enable.
When SPLIT = ‘1’, the selected endpoint FIFO is split. The upper half of the selected FIFO is
used by the IN endpoint; the lower half of the selected FIFO is used by the OUT endpoint.
ISO
R/W
Bit6
DIRSEL
R/W
Bit5
Bit4
R
-
C8051F340/1/2/3/4/5/6/7/8/9
Rev. 1.1
FCDT
R/W
Bit3
SPLIT
R/W
Bit2
Bit1
R
-
Bit0
R
-
USB Address:
00000000
Reset Value
0x12
199
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