R5F21272SDFP#U0 Renesas Electronics America, R5F21272SDFP#U0 Datasheet - Page 300
R5F21272SDFP#U0
Manufacturer Part Number
R5F21272SDFP#U0
Description
IC R8C/27 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/27r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21272SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21272SDFP#U0R5F21272SDFP#V2
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 16.17
NOTE:
(4)
(5)
(1)
(2)
(3)
(6)
Sep 26, 2008
1. Write 0 after reading 1 to set the TEND bit to 0.
SSSR register
SSER register
Communication Mode)
Sample Flowchart for Data Transmission/Reception (Clock Synchronous
Write transmit data to SSTDR register
Read receive data in SSRDR register
Read TDRE bit in SSSR register
Read RDRF bit in SSSR register
Read TEND bit in SSSR register
No
Page 281 of 453
RDRF = 1 ?
TEND = 1 ?
Initialization
TDRE = 1 ?
transmission
continues?
Start
Data
End
TEND bit ← 0
RE bit ← 0
TE bit ← 0
Yes
Yes
No
Yes
No
No
(1)
Yes
(2) Confirm that the RDRF bit is set to 1. If the RDRF
(3) Determine whether the data transmission
(4) When the data transmission is completed, the
(5) Set the TEND bit to 0 and bits RE and TE in
(6) the SSER register to 0 before ending transmit/
(1) After reading the SSSR register and confirming
bit is set to 1, read the receive data in the SSRDR
register. When reading the SSRDR register is
read, the RDRF bit is automatically set to 0.
continues
TEND bit in the SSSR register is set to 1.
receive mode.
that the TDRE bit is set to 1, write the transmit
data to the SSTDR register. When the transmit
data is written to the SSTDR register, the TDRE
bit is automatically set to 0.
16. Clock Synchronous Serial Interface
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