C8051F366-GQ Silicon Laboratories Inc, C8051F366-GQ Datasheet - Page 140

• Manufacturer Part Number: C8051F366-GQ
• Description: IC 8051 MCU 32K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F366-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• On-chip Dac: 1-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051F36x
• Maximum Speed: 50 MHz
• Operating Supply Voltage: 3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1648

C8051F360/1/2/3/4/5/6/7/8/9
13.3. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of V
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the V
enabled as a reset source on C8051F36x devices for the Flash to be successfully modified. If either the
V
erated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.3.1.
140
DD
Monitor or the V
V
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
2. Make certain that the minimum V
3. Keep the on-chip V
4. As an added precaution, explicitly enable the V
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
DD
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
meet this rise time specification, then add an external V
the device that holds the device in reset until V
drops below V
more information on the VDD Monitor Threshold voltage (V
in code as possible. This should be the first set of instructions executed after the Reset Vector.
For 'C'-based systems, this will involve modifying the startup code added by the 'C' compiler.
See your compiler documentation for more details. Make certain that there are no delays in
software between enabling the V
Code examples showing this can be found in AN201, "Writing to Flash from Firmware", avail-
able from the Silicon Laboratories web site.
Note: On C8051F36x devices, both the V
be enabled to write or erase Flash without generating a Flash Error Device Reset.
reset source inside the functions that write and erase Flash memory. The V
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
Maintenance and the
DD
DD
, system clock frequency, or temperature. This accidental execution of Flash modi-
Monitor reset source is not enabled, a Flash Error Device Reset will be gen-
RST
. Please see Table 12.1, “Reset Electrical Characteristics,” on page 134 for
DD
Monitor enabled and enable the V
V
DD
Monitor
DD
DD
rise time specification of 1 ms is met. If the system cannot
Monitor and enabling the V
Rev. 1.0
DD
Monitor and the V
DD
DD
reaches V
Monitor and enable the V
DD
DD
RST
brownout circuit to the /RST pin of
Monitor as a reset source as early
DD
RST
).
Monitor must be enabled and
DD
DD
and re-asserts /RST if V
Monitor as a reset source.
Monitor reset source must
DD
DD
Monitor enable
Monitor as a
DD