C8051F500-IQ Silicon Laboratories Inc, C8051F500-IQ Datasheet - Page 310
![IC 8051 MCU 64K FLASH 48-QFP](/photos/12/17/121756/c8051f500-iq_sml.jpg)
C8051F500-IQ
Manufacturer Part Number
C8051F500-IQ
Description
IC 8051 MCU 64K FLASH 48-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F500-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
48-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Package
48PQFP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1530 - ADAPTER PROG TOOLSTICK F500336-1529 - PLATFORM PROG TOOLSTCK F500336-1527 - KIT DEV FOR C8051F50X336-1526 - BOARD PROTOTYPE W/C8051F500
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1510
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F500-IQ
Manufacturer:
SiliconL
Quantity:
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Company:
Part Number:
C8051F500-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
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Part Number:
C8051F500-IQR
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C8051F50x/F51x
D
Revision 0.2 to Revision 1.0
Revision 1.0 to Revision 1.1
Note: All items from the C8051F50x-F51x Errata dated July 1, 2009 are incorporated into this data sheet.
310
OCUMENT
Added documentation for 40-pin QFN devices in all relevant chapters.
Change oscillator specification for devices initially specified to have ±1.0% oscillators. All devices are
now rated for ±0.5% across operating voltage and temperature.
Removed all content from “1. System Overview”after block diagrams.
Updated “5. Electrical Characteristics”—Updated various specifications and filled in all TBD values for
all specifications.
Updated “Table 5.11. Voltage Reference Electrical Characteristics”—Changed Minimum external
reference input voltage from 0 V to 1 V.
Updated “9. Comparators”—Fixed incorrect references to SFR Definitions 7.x.
Updated “Table 13.1”—Added SFRs SN0, SN1, SN2, and SN3 to SFR map.
Updated “SFR Definition 19.2” (OSCICN) - Removed errant row for Bit 6. Also, Bit 3 defintion changed
to a Reserved bit from an Unused bit.
Updated “20. Port Input/Output”—Added Port 4 to the crossbar diagrams and documentation.
Updated “27.4. Watchdog Timer Mode”—Fixed incorrect references from Module 2 as the watchdog
module to Module 5.
Updated “Ordering Information” on page 20 and Table 2.1, “Product Selection Guide,” on page 21 to
include -A (Automotive) devices and automotive qualification information.
Updated supply current related specifications throughout “5. Electrical Characteristics”.
Updated SFR Definition 8.1 to change VREF high setting to 2.20 V from 2.25 V.
Updated Table 5.12 on page 51 and Figure 9.1 on page 75 to indicate that Comparators are powered
from V
Updated Table 5.12 on page 51 to fix Comparator Supply Current Typical values for Modes 2 and 3.
Updated the Gain Table in “6.3.1. Calculating the Gain Value” to fix the ADC0GNH Value in the last row.
Updated Table 11.1 on page 89 with correct timing for all branch instructions, MOVC, and CPL A.
Updated “15.1. Programming the Flash Memory” to clarify behavior of 8-bit MOVX instructions and
when writing/erasing Flash.
Updated SFR Definition 15.3 to include FLEWT bit definition. This bit must be set before writing or
erasing Flash. Also updated Table 5.5 to reflect new Flash Write and Erase timing.
Updated “17.7. Flash Error Reset” with an additional cause of a Flash Error reset.
Updated “20.1.3. Interfacing Port I/O in a Multi-Voltage System” to remove note regarding interfacing to
voltages above VIO.
Updated “23. SMBus”to remove all hardware ACK features, including SMB0ADM and SMB0ADR
SFRs.
Updated “24.3.2. Data Reception” to clarify UART receive FIFO behavior.
Updated SFR Definition 24.1 for SCON0 to correct SFR Page to 0x00 from All Pages.
IO
and not V
C
HANGE
DDA
.
L
IST
Rev. 1.2
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