C8051F368-GQ Silicon Laboratories Inc, C8051F368-GQ Datasheet - Page 267

• Manufacturer Part Number: C8051F368-GQ
• Description: IC 8051 MCU 16K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F36xr

Specifications of C8051F368-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 29
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 21x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F360DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 21 Channel
• On-chip Dac: 10 bit, 1 Channel
• For Use With: 770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1410 - KIT DEV FOR C8051F360 FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1650

22.2.1. Edge-triggered Capture Mode
In this mode, a valid transition on the CEXn pin causes PCA0 to capture the value of the PCA0 counter/
timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and
PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of transi-
tion that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative edge),
or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag (CCFn)
in PCA0CN is set to logic ‘1’ and an interrupt request is generated if CCF interrupts are enabled. The
CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt service routine,
and must be cleared by software. If both CAPPn and CAPNn bits are set to logic ‘1’, then the state of the
Port pin associated with CEXn can be read directly to determine whether a rising-edge or falling-edge
caused the capture.
Note: The signal at CEXn must be high or low for at least 2 system clock cycles to be recognized by the
hardware.
PWM16 ECOM CAPP CAPN MAT
Port I/O
X
X
X
X
X
X
0
1
Table 22.2. PCA0CPM Register Settings for PCA Capture/Compare Modules
X = Don’t Care
X
X
X
1
1
1
1
1
Crossbar
1
0
1
0
0
0
0
0
Figure 22.4. PCA Capture Mode Diagram
CEXn
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
TOG
0
0
0
0
1
1
0
0
W
P
M
1
6
n
PCA0CPMn
C
O
M
E
n
C8051F360/1/2/3/4/5/6/7/8/9
Rev. 1.0
C
A
P
P
n
PWM ECCF
C
A
P
N
n
0
1
0
0
0
0
0
1
1
1
M
A
T
n
O
G
T
n
W
P
M
n
C
C
E
F
n
0
1
X
X
X
X
X
X
0
0
C
F
C
R
Capture triggered by negative edge on
PCA0CN
Capture triggered by positive edge on
C
C
F
5
Capture triggered by transition on
C
C
F
4
PCA
Timebase
C
C
F
3
16-Bit Pulse Width Modulator
8-Bit Pulse Width Modulator
C
C
F
2
C
C
F
1
PCA Interrupt
C
C
F
0
High Speed Output
Frequency Output
Operation Mode
Capture
Software Timer
PCA0CPLn
PCA0L
CEXn
CEXn
CEXn
PCA0CPHn
PCA0H
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