C8051F502-IQ Silicon Laboratories Inc, C8051F502-IQ Datasheet - Page 187
![IC 8051 MCU 64K FLASH 32-QFP](/photos/12/17/121746/c8051f502-iq_sml.jpg)
C8051F502-IQ
Manufacturer Part Number
C8051F502-IQ
Description
IC 8051 MCU 64K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Datasheets
1.C8051F507-IM.pdf
(312 pages)
2.C8051F502-IM.pdf
(1 pages)
3.C8051F503-IM.pdf
(312 pages)
Specifications of C8051F502-IQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
32-QFP
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 32 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1559 - KIT REF DESIGN CAN DIAGNOSTIC336-1532 - ADAPTER PROG TOOLSTICK F502336-1531 - PLATFORM PROG TOOLSTCK F502336-1528 - DAUGHTER CARD TOOLSTICK F500336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1514
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F502-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F502-IQR
Manufacturer:
RUBYCON
Quantity:
20 000
Company:
Part Number:
C8051F502-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
- Current page: 187 of 312
- Download datasheet (3Mb)
20.5. Port Match
Port match functionality allows system events to be triggered by a logic value change on P0, P1, P2 or P3.
A software controlled value stored in the PnMATCH registers specifies the expected or normal logic values
of P0, P1, P2, and P3. A Port mismatch event occurs if the logic levels of the Port’s input pins no longer
match the software controlled value. This allows Software to be notified if a certain change or pattern
occurs on P0, P1, P2, or P3 input pins regardless of the XBRn settings.
The PnMASK registers can be used to individually select which of the port pins should be compared
against the PnMATCH registers. A Port mismatch event is generated if (Pn & PnMASK) does not equal
(PnMATCH & PnMASK), where n is 0, 1, 2 or 3
A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Definition 20.4. P0MASK: Port 0 Mask Register
SFR Address = 0xF2; SFR Page = 0x00
SFR Definition 20.5. P0MAT: Port 0 Match Register
SFR Address = 0xF1; SFR Page = 0x00
Reset
Reset
Name
Name
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P0MASK[7:0]
P0MAT[7:0]
Name
Name
7
0
7
1
Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MAT which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
0
1
6
6
5
0
5
1
Rev. 1.1
P0MASK[7:0]
4
0
4
1
P0MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
C8051F50x-F51x
2
0
2
1
1
0
1
1
0
0
0
1
187
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