C8051F920-GQ Silicon Laboratories Inc, C8051F920-GQ Datasheet - Page 57

• Manufacturer Part Number: C8051F920-GQ
• Description: IC 8051 MCU 32K FLASH 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F9xxr

Specifications of C8051F920-GQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 24
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 3.6 V
• Data Converters: A/D 23x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F9x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: UART, SPI, SMBus
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 0.9 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F930DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 23-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1473 - KIT DEV C8051F920,F921,F930,F931
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1469

Table 4.4. Reset Electrical Characteristics
V
RST Output Low Voltage
RST Input High Voltage
RST Input Low Voltage
RST Input Pullup Current
VDD/DC+ Monitor Thresh-
old (V
VBAT Ramp Time for
Power On
VBAT Monitor Threshold
(V
Missing Clock Detector
Timeout
Minimum System Clock w/
Missing Clock Detector
Enabled
Reset Time Delay
Minimum RST Low Time to
Generate a System Reset
V
V
Current
DD
DD
DD
POR
= 1.8 to 3.6 V, –40 to +85 °C unless otherwise specified.
Monitor Turn-on Time
Monitor Supply 
RST
)
Parameter
)
I
V
V
V
V
RST = 0.0 V, VDD = 1.8 V
RST = 0.0 V, VDD = 3.6 V
Early Warning
Reset Trigger
(all power modes except Sleep)
VBAT Ramp from 0–0.9 V
Initial Power-On (VBAT Rising)
Brownout Condition (VBAT Falling)
Recovery from Brownout (VBAT Rising)
Time from last system clock rising edge
to reset initiation
System clock frequency which triggers
a missing clock detector timeout
Delay between release of any reset
source and code 
execution at location 0x0000
OL
DD
DD
DD
DD
= 1.4 mA,
= 2.0 to 3.6 V
= 0.9 to 2.0 V
= 2.0 to 3.6 V
= 0.9 to 2.0 V
Conditions
Rev. 1.1
C8051F93x-C8051F92x
V
0.7 x V
DD
Min
100
1.8
1.7
0.7
15
—
—
—
—
—
—
—
—
—
—
—
—
– 0.6
DD
1.85
1.75
0.75
0.95
Typ
650
300
0.8
—
—
—
—
—
20
—
10
—
4
7
7
0.3 x V
1000
Max
0.6
0.6
1.9
1.8
0.9
30
10
—
—
—
—
—
—
—
—
—
3
DD
Units
kHz
µA
ms
µA
µs
µs
µs
ns
V
V
V
V
V
V
V
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