C8051F507-IM Silicon Laboratories Inc, C8051F507-IM Datasheet - Page 62

• Manufacturer Part Number: C8051F507-IM
• Description: IC 8051 MCU 32K FLASH 32-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F507-IM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• A/d Bit Size: 12 bit
• A/d Channels Available: 32
• Height: 0.83 mm
• Length: 5 mm
• Supply Voltage (max): 5.25 V
• Supply Voltage (min): 1.8 V
• Width: 5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1525-5

C8051F50x/F51x
Gain Register Definition 6.3. ADC0GNA: ADC0 Additional Selectable Gain
Indirect Address = 0x08;
62
Note : This register is accessed indirectly; See Section 6.3.2 for details for writing this register.
Name Reserved
Reset
7:1
Bit
Type
0
Bit
GAINADD
Reserved
Name
W
7
0
Must Write 0000000b.
ADC0 Additional Gain Bit.
Setting this bit add 1/64 (0.016) gain to the gain value in the ADC0GNH and
ADC0GNL registers.
Reserved
W
6
0
Reserved
W
5
0
Reserved
Rev. 1.2
W
4
0
Function
Reserved
W
3
0
Reserved
W
2
0
Reserved GAINADD
W
1
0
W
0
1