C8051F311-GM Silicon Laboratories Inc, C8051F311-GM Datasheet
C8051F311-GM
Specifications of C8051F311-GM
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C8051F311-GM Summary of contents
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... External oscillator: Crystal, RC clock ( MHz; pin modes) 11 µ kHz - Can switch between clock sources on-the-fly; useful 0.1 µA in power saving modes –40 to +85 °C Packages - 32-pin LQFP (C8051F310/2/4) - 28-pin MLP (C8051F311/3/5) ANALOG DIGITAL I/O PERIPHERALS UART SMBus 10-bit + SPI 200ksps - PCA ADC ...
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C8051F310/1/2/3/4/5 2 Notes Rev. 1.5 ...
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Table Of Contents 1. System Overview.................................................................................................... 17 1.1. CIP-51™ Microcontroller Core.......................................................................... 25 1.1.1. Fully 8051 Compatible.............................................................................. 25 1.1.2. Improved Throughput ............................................................................... 25 1.1.3. Additional Features .................................................................................. 26 1.2. On-Chip Memory............................................................................................... 27 1.3. On-Chip Debug Circuitry................................................................................... 28 1.4. Programmable Digital I/O ...
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C8051F310/1/2/3/4/5 8.3.4. Interrupt Latency ...................................................................................... 87 8.3.5. Interrupt Register Descriptions................................................................. 89 8.4. Power Management Modes .............................................................................. 94 8.4.1. Idle Mode.................................................................................................. 94 8.4.2. Stop Mode ................................................................................................ 95 9. Reset Sources......................................................................................................... 97 9.1. Power-On Reset ............................................................................................... 98 9.2. Power-Fail Reset / VDD ...
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Transfer Modes.................................................................................. 147 14.5.1.Master Transmitter Mode ....................................................................... 147 14.5.2.Master Receiver Mode ........................................................................... 148 14.5.3.Slave Receiver Mode ............................................................................. 149 14.5.4.Slave Transmitter Mode ......................................................................... 150 14.6.SMBus Status Decoding................................................................................. 151 15. UART0.................................................................................................................... 153 15.1.Enhanced Baud Rate Generation................................................................... 154 15.2.Operational Modes ......................................................................................... 155 ...
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C8051F310/1/2/3/4/5 18.3.1.Watchdog Timer Operation .................................................................... 202 18.3.2.Watchdog Timer Usage ......................................................................... 203 18.4.Register Descriptions for PCA........................................................................ 205 19. Revision Specific Behavior ................................................................................. 211 19.1.Revision Identification..................................................................................... 211 19.2.Reset Behavior ............................................................................................... 211 19.2.1.Weak Pullups on GPIO Pins .................................................................. 211 19.2.2.VDD Monitor and the ...
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... List of Figures 1. System Overview Figure 1.1. C8051F310 Block Diagram .................................................................... 19 Figure 1.2. C8051F311 Block Diagram .................................................................... 20 Figure 1.3. C8051F312 Block Diagram .................................................................... 21 Figure 1.4. C8051F313 Block Diagram .................................................................... 22 Figure 1.5. C8051F314 Block Diagram .................................................................... 23 Figure 1.6. C8051F315 Block Diagram .................................................................... 24 Figure 1.7. Comparison of Peak MCU Execution Speeds ....................................... 25 Figure 1 ...
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C8051F310/1/2/3/4/5 9. Reset Sources Figure 9.1. Reset Sources........................................................................................ 97 Figure 9.2. Power-On and VDD Monitor Reset Timing ............................................ 98 10. Flash Memory Figure 10.1. Flash Program Memory Map.............................................................. 105 11. External RAM 12. Oscillators Figure 12.1. Oscillator Diagram.............................................................................. 111 Figure ...
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Figure 17.3. T0 Mode 3 Block Diagram.................................................................. 180 Figure 17.4. Timer 2 16-Bit Mode Block Diagram .................................................. 185 Figure 17.5. Timer 2 8-Bit Mode Block Diagram .................................................... 186 Figure 17.6. Timer 3 16-Bit Mode Block Diagram .................................................. 189 Figure 17.7. ...
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C8051F310/1/2/3/4/5 10 Notes Rev. 1.5 ...
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List of Tables 1. System Overview Table 1.1. Product Selection Guide ......................................................................... 18 2. Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings .................................................................... 33 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics ....................................................... 34 4. Pinout and ...
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C8051F310/1/2/3/4/5 Table 15.4. Timer Settings for Standard Baud Rates Using an External 18.432 MHz Oscillator ........................................................................ 161 Table 15.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Oscillator ...................................................................... 162 Table 15.6. Timer Settings for Standard Baud ...
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List of Registers SFR Definition 5.1. AMX0P: AMUX0 Positive Channel Select . . . . . . . . . . . . . . . . . . . 50 SFR Definition 5.2. AMX0N: AMUX0 Negative Channel Select . ...
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C8051F310/1/2/3/4/5 SFR Definition 13.5. P0MDOUT: Port0 Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . 127 SFR Definition 13.6. P0SKIP: Port0 Skip ...
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SFR Definition 18.7. PCA0CPHn: PCA Capture Module High Byte . . . . . . . . . . . . . . 209 C2 Register Definition 20.1. C2ADD: C2 Address . . . . . . . . . ...
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C8051F310/1/2/3/4/5 16 Notes Rev. 1.5 ...
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System Overview C8051F31x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are listed below. Refer to Table 1.1 for specific product feature selection. • High-speed pipelined 8051-compatible microcontroller core ( MIPS) • In-system, full-speed, non-intrusive debug ...
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... C8051F310/1/2/3/4/5 Table 1.1. Product Selection Guide C8051F310 25 16 1280 C8051F311 25 16 1280 C8051F312 25 8 1280 C8051F313 25 8 1280 C8051F314 25 8 1280 C8051F315 25 8 1280 Rev. 1.5 2 LQFP-32 2 MLP-28 2 LQFP-32 2 MLP-28 2 LQFP-32 2 MLP-28 ...
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Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.1. C8051F310 Block Diagram C8051F310/1/2/3/4/5 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 ...
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... C8051F310/1/2/3/4/5 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.2. C8051F311 Block Diagram 20 Port 0 Latch Port 1 Latch UART 8 16kbyte Timer FLASH 0 0,1,2,3 / RTC 5 256 byte Reset SRAM PCA/ 1 WDT ...
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Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.3. C8051F312 Block Diagram C8051F310/1/2/3/4/5 Port 0 Latch Port 1 Latch UART Timer FLASH ...
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C8051F310/1/2/3/4/5 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.4. C8051F313 Block Diagram 22 Port 0 Latch Port 1 Latch UART Timer FLASH ...
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Analog/Digital Power VDD GND C2D Debug HW Reset /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.5. C8051F314 Block Diagram C8051F310/1/2/3/4/5 Port 0 Latch Port 1 Latch UART Timer FLASH ...
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C8051F310/1/2/3/4/5 Analog/Digital Power VDD GND C2D Debug HW /RST/C2CK Brown- POR Out External XTAL1 Oscillator System Clock XTAL2 Circuit 2% Internal Oscillator Figure 1.6. C8051F315 Block Diagram 24 Port 0 Latch Port 1 Latch UART Timer FLASH ...
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CIP-51™ Microcontroller Core 1.1.1. Fully 8051 Compatible The C8051F31x family utilizes Silicon Labs' proprietary CIP-51 microcontroller core. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop software. The ...
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C8051F310/1/2/3/4/5 1.1.3. Additional Features The C8051F31x SoC family includes several key enhancements to the CIP-51 core and peripherals to improve performance and ease of use in end applications. The extended interrupt handler provides 14 interrupt sources into the CIP-51 (as ...
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On-Chip Memory The CIP-51 has a standard 8051 program and data address configuration. It includes 256 bytes of data RAM, with the upper 128 bytes dual-mapped. Indirect addressing accesses the upper 128 bytes of general purpose RAM, and direct ...
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C8051F310/1/2/3/4/5 1.3. On-Chip Debug Circuitry The C8051F31x devices include on-chip Silicon Labs 2-Wire (C2) debug circuitry that provides non-intru- sive, full speed, in-circuit debugging of the production part installed in the end application. Silicon Labs' debugging system supports inspection and ...
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... Programmable Digital I/O and Crossbar C8051F310/2/4 devices include 29 I/O pins (three byte-wide Ports and one 5-bit-wide Port); C8051F311/3/5 devices include 25 I/O pins (three byte-wide Ports and one 1-bit-wide Port). The C8051F31x Ports behave like typical 8051 Ports with a few enhancements. Each Port pin may be config- ured as an analog input or a digital I/O pin. Pins selected as digital I/Os may additionally be configured for push-pull or open-drain output. The “ ...
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C8051F310/1/2/3/4/5 1.5. Serial Ports The C8051F31x Family includes an SMBus/I2C interface, a full-duplex UART with enhanced baud rate configuration, and an Enhanced SPI interface. Each of the serial buses is fully implemented in hardware and makes extensive use of the ...
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Analog to Digital Converter The C8051F310/1/2/3 devices include an on-chip 10-bit SAR ADC with a 25-channel differential input mul- tiplexer. With a maximum throughput of 200 ksps, the ADC offers true 10-bit accuracy with an INL of ±1LSB. ...
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C8051F310/1/2/3/4/5 1.8. Comparators C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be routed to a Port ...
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Absolute Maximum Ratings Table 2.1. Absolute Maximum Ratings Parameter Ambient temperature under bias Storage Temperature Voltage on any Port I/O Pin or RST with respect to GND Voltage on V with respect to GND DD Maximum Total current through ...
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C8051F310/1/2/3/4/5 3. Global DC Electrical Characteristics Table 3.1. Global DC Electrical Characteristics –40°C to +85°C, 25 MHz System Clock unless otherwise specified. Parameter Digital Supply Voltage Digital Supply Current with V DD CPU active V V Digital Supply Current with ...
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Pinout and Package Definitions Table 4.1. Pin Definitions for the C8051F31x Pin Numbers Name ‘F310/2/4 ‘F311/3 GND 3 3 RST C2CK P3. C2D P0. VREF P0 P0.2/ ...
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C8051F310/1/2/3/4/5 Table 4.1. Pin Definitions for the C8051F31x (Continued) Pin Numbers Name ‘F310/2/4 ‘F311/3 P2.3 15 ...
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P0 GND 4 VDD /RST/C2CK 5 6 P3.0/C2D 7 P3.1 8 P3.2 Figure 4.1. LQFP-32 Pinout Diagram (Top View) C8051F310/1/2/3/4/5 C8051F310/2/4 Top View Rev. 1.5 24 P1.2 23 P1.3 22 P1.4 21 P1.5 20 P1.6 19 ...
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C8051F310/1/2/3/4 PIN 1 IDENTIFIER Figure 4.2. LQFP-32 Package Diagram 38 Table 4.2. LQFP-32 Package Dimensions MIN 0.05 A2 1. ...
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... GND P0.1 1 P0.0 2 GND 3 C8051F311/3/5 VDD 4 /RST/C2CK 5 P3.0/C2D 6 P2.7 7 Figure 4.3. MLP-28 Pinout Diagram (Top View) C8051F310/1/2/3/4/5 Top View GND Rev. 1.5 21 P1.1 20 P1.2 19 P1.3 18 P1.4 17 P1.5 16 P1.6 15 P1.7 39 ...
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C8051F310/1/2/3/4/5 Bottom View DETAIL Side View DETAIL 1 Figure 4.4. MLP-28 Package Drawing ...
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Optional GND Connection L 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.5. Typical MLP-28 Landing Diagram C8051F310/1/2/3/4/5 Top View E2 E Rev. 1.5 0. ...
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C8051F310/1/2/3/4/5 0.50 mm 0.60 mm 0. 0.20 mm 0.30 mm 0.50 mm 0.35 mm 0.10 mm 0.85 mm Figure 4.6. MLP-28 Solder Paste Recommendation 42 Top View 0.60 mm 0.30 mm 0. ...
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ADC (ADC0, C8051F310/1/2/3 only) The ADC0 subsystem for the C8051F310/1/2/3 consists of two analog multiplexers (referred to collectively as AMUX0) with 25 total input selections, and a 200 ksps, 10-bit successive-approximation-register ADC with integrated track-and-hold and programmable window ...
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C8051F310/1/2/3/4/5 5.1. Analog Multiplexer AMUX0 selects the positive and negative inputs to the ADC. Any of the following may be selected as the positive input: P1.0-P3.4, the on-chip temperature sensor, or the positive power supply (V following may be selected ...
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Temperature Sensor The typical temperature sensor transfer function is shown in Figure 5.2. The output voltage (V positive ADC input when the temperature sensor is selected by bits AMX0P4-0 in register AMX0P. (mV) 1200 1100 1000 900 800 700 ...
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C8051F310/1/2/3/4/5 5.00 4.00 3.00 2.00 1.00 0.00 -40.00 -20.00 -1.00 -2.00 -3.00 -4.00 -5.00 Figure 5.3. Temperature Sensor Error with 1-Point Calibration 46 40.00 0.00 20.00 Temperature (degrees C) Rev. 1.5 5.00 4.00 3.00 2.00 1.00 0.00 60.00 80.00 -1.00 ...
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Modes of Operation ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by (AD0SC + ...
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C8051F310/1/2/3/4/5 5.3.2. Tracking Modes According to Table 5.1, each ADC0 conversion must be preceded by a minimum tracking time for the con- verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its ...
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Settling Time Requirements When the ADC0 input configuration is changed (i.e., a different AMUX0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, ...
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... C8051F310/2; selection RESERVED on C8051F311/3 devices. 50 R/W R/W R/W AMX0P4 AMX0P3 AMX0P2 AMX0P1 Bit4 Bit3 Bit2 ADC0 Positive Input P1.0 P1.1 P1 ...
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... GND (ADC in Single-Ended Mode) †Only applies to C8051F310/2; selection RESERVED on C8051F311/3 devices. C8051F310/1/2/3/4/5 R/W R/W R/W AMX0N4 AMX0N3 AMX0N2 AMX0N1 AMX0N0 00000000 Bit4 Bit3 Bit2 ADC0 Negative Input P1 ...
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C8051F310/1/2/3/4/5 SFR Definition 5.3. ADC0CF: ADC0 Configuration R/W R/W R/W AD0SC4 AD0SC3 AD0SC2 Bit7 Bit6 Bit5 Bits7-3: AD0SC4-0: ADC0 SAR Conversion Clock Period Bits. SAR Conversion clock is derived from system clock by the following equation, where AD0SC refers to ...
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SFR Definition 5.6. ADC0CN: ADC0 Control R/W R/W R/W AD0EN AD0TM AD0INT AD0BUSY AD0WINT AD0CM2 AD0CM1 AD0CM0 00000000 Bit7 Bit6 Bit5 Bit7: AD0EN: ADC0 Enable Bit. 0: ADC0 Disabled. ADC0 is in low-power shutdown. 1: ADC0 Enabled. ADC0 is active ...
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C8051F310/1/2/3/4/5 5.4. Programmable Window Detector The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-pro- grammed limits, and notifies the system when a desired condition is detected. This is especially effective in an interrupt-driven system, saving code ...
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SFR Definition 5.9. ADC0LTH: ADC0 Less-Than Data High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: High byte of ADC0 Less-Than Data Word. SFR Definition 5.10. ADC0LTL: ADC0 Less-Than Data Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Low ...
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C8051F310/1/2/3/4/5 5.4.1. Window Detector In Single-Ended Mode Figure 5.6 shows two example window comparisons for right-justified, single-ended data, with ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). In single-ended mode, the input voltage can range from ‘0’ to VREF ...
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Window Detector In Differential Mode Figure 5.8 shows two example window comparisons for right-justified, differential data, with ADC0LTH:ADC0LTL = 0x0040 (+64d) and ADC0GTH:ADC0GTH = 0xFFFF (-1d). In differential mode, the measurable voltage between the input pins is between -VREF ...
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C8051F310/1/2/3/4/5 Table 5.1. ADC0 Electrical Characteristics V = 3.0 V, VREF = 2.40 V (REFSL=0), –40 to +85 °C unless otherwise specified DD Parameter DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Full Scale Error Offset Temperature Coefficient Dynamic ...
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Voltage Reference (C8051F310/1/2/3 only) The voltage reference MUX on C8051F310/1/2/3 devices is configurable to use an externally connected voltage reference, or the power supply voltage (see Figure 6.1). The REFSL bit in the Reference Control register (REF0CN) selects the ...
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C8051F310/1/2/3/4/5 SFR Definition 6.1. REF0CN: Reference Control R/W R/W R/W Bit7 Bit6 Bit5 Bits7-4: UNUSED. Read = 0000b; Write = don’t care. Bit3: REFSL: Voltage Reference Select. This bit selects the source for the internal voltage reference. 0: VREF input ...
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Comparators C8051F31x devices include two on-chip programmable voltage comparators: Comparator0 is shown in Figure 7.1; Comparator1 is shown in Figure 7.2. The two comparators operate identically with the following exceptions: (1) Their input selections differ as shown in Figure ...
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C8051F310/1/2/3/4/5 The Comparator output can be polled in software, used as an interrupt source, and/or routed to a Port pin. When routed to a Port pin, the Comparator output is available asynchronous or synchronous to the system clock; the asynchronous ...
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CP0+ VIN+ CP0- VIN- CIRCUIT CONFIGURATION Positive Hysteresis Voltage (Programmed with CP0HYP Bits) VIN- INPUTS VIN+ OUTPUT V OL Positive Hysteresis Disabled Figure 7.3. Comparator Hysteresis Plot The Comparator hysteresis is software-programmable via its Comparator Control register CPTnCN (for n ...
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C8051F310/1/2/3/4/5 SFR Definition 7.1. CPT0CN: Comparator0 Control R/W R R/W CP0EN CP0OUT CP0RIF Bit7 Bit6 Bit5 Bit7: CP0EN: Comparator0 Enable Bit. 0: Comparator0 Disabled. 1: Comparator0 Enabled. Bit6: CP0OUT: Comparator0 Output State Flag. 0: Voltage on CP0+ < CP0-. 1: ...
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SFR Definition 7.2. CPT0MX: Comparator0 MUX Selection R/W R/W R CMX0N1 CMX0N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits5-4: CMX0N1-CMX0N0: Comparator0 Negative Input MUX Select. These bits select which Port pin is ...
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C8051F310/1/2/3/4/5 SFR Definition 7.3. CPT0MD: Comparator0 Mode Selection R/W R/W R CP0RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b. Write = don’t care. Bit5: CP0RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled. 1: Comparator rising-edge ...
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SFR Definition 7.4. CPT1CN: Comparator1 Control R/W R R/W CP1EN CP1OUT CP1RIF Bit7 Bit6 Bit5 Bit7: CP1EN: Comparator1 Enable Bit. 0: Comparator1 Disabled. 1: Comparator1 Enabled. Bit6: CP1OUT: Comparator1 Output State Flag. 0: Voltage on CP1+ < CP1–. 1: Voltage ...
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C8051F310/1/2/3/4/5 SFR Definition 7.5. CPT1MX: Comparator1 MUX Selection R/W R/W R CMX1N1 CMX1N0 Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bits5-4: CMX1N1-CMX1N0: Comparator1 Negative Input MUX Select. These bits select which Port pin ...
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SFR Definition 7.6. CPT1MD: Comparator1 Mode Selection R/W R/W R CP1RIE Bit7 Bit6 Bit5 Bits7-6: UNUSED. Read = 00b, Write = don’t care. Bit5: CP1RIE: Comparator Rising-Edge Interrupt Enable. 0: Comparator rising-edge interrupt disabled 1: Comparator rising-edge interrupt ...
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C8051F310/1/2/3/4/5 Table 7.1. Comparator Electrical Characteristics V = 3.0 V, –40 to +85 °C unless otherwise noted. DD All specifications apply to both Comparator0 and Comparator1 unless otherwise noted. Parameter Response Time: † Mode 0, Vcm = 1.5 V Response ...
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CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset ...
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C8051F310/1/2/3/4/5 Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture standard 8051, all instructions except for MUL and DIV take system clock cycles to execute, ...
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Instruction Set The instruction set of the CIP-51 System Controller is fully compatible with the standard MCS-51™ instruc- tion set. Standard 8051 development tools can be used to develop software for the CIP-51. All CIP-51 instructions are the binary ...
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C8051F310/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description DEC Rn Decrement register DEC direct Decrement direct byte DEC @Ri Decrement indirect RAM INC DPTR Increment Data Pointer MUL AB Multiply A and B DIV AB Divide A by ...
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Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description MOV direct, #data Move immediate to direct byte MOV @Ri, A Move A to indirect RAM MOV @Ri, direct Move direct byte to indirect RAM MOV @Ri, #data Move immediate to ...
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C8051F310/1/2/3/4/5 Table 8.1. CIP-51 Instruction Set Summary (Continued) Mnemonic Description JNZ rel Jump if A does not equal zero CJNE A, direct, rel Compare direct byte to A and jump if not equal CJNE A, #data, rel Compare immediate to ...
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Memory Organization The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are two separate memory spaces: program memory and data memory. Program and data memory share the same address space but ...
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C8051F310/1/2/3/4/5 8.2.2. Data Memory The CIP-51 includes 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The lower 128 bytes of data memory are used for general purpose registers and scratch pad mem- ory. ...
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Special Function Registers The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The CIP-51 duplicates the SFRs found in a ...
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C8051F310/1/2/3/4/5 Table 8.3. Special Function Registers Register Address Description SFRs are listed in alphabetical order. All undefined SFR locations are reserved ACC 0xE0 Accumulator ADC0CF 0xBC ADC0 Configuration ADC0CN 0xE8 ADC0 Control ADC0GTH 0xC4 ADC0 Greater-Than Compare High ADC0GTL 0xC3 ...
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Table 8.3. Special Function Registers (Continued) Register Address Description P2SKIP 0xD6 Port 2 Skip P3 0xB0 Port 3 Latch P3MDIN 0xF4 Port 3 Input Mode Configuration P3MDOUT 0xA7 Port 3 Output Mode Configuration PCA0CN 0xD8 PCA Control PCA0CPH0 0xFC PCA ...
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C8051F310/1/2/3/4/5 Table 8.3. Special Function Registers (Continued) Register Address Description TMR2L 0xCC Timer/Counter 2 Low TMR2RLH 0xCB Timer/Counter 2 Reload High TMR2RLL 0xCA Timer/Counter 2 Reload Low TMR3CN 0x91 Timer/Counter 3Control TMR3H 0x95 Timer/Counter 3 High TMR3L 0x94 Timer/Counter 3Low ...
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SFR Definition 8.2. DPH: Data Pointer High Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: DPH: Data Pointer High. The DPH register is the high byte of the 16-bit DPTR. DPTR is used to access indirectly addressed Flash memory. SFR ...
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C8051F310/1/2/3/4/5 SFR Definition 8.4. PSW: Program Status Word R/W R/W R Bit7 Bit6 Bit5 Bit7: CY: Carry Flag. This bit is set when the last arithmetic operation resulted in a carry (addition borrow (subtraction). It ...
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SFR Definition 8. Register R/W R/W R/W B.7 B.6 B.5 Bit7 Bit6 Bit5 Bits7- Register. This register serves as a second accumulator for certain arithmetic operations. C8051F310/1/2/3/4/5 R/W R/W R/W R/W B.4 B.3 B.2 B.1 Bit4 ...
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C8051F310/1/2/3/4/5 8.3. Interrupt Handler The CIP-51 includes an extended interrupt system supporting a total of 14 interrupt sources with two prior- ity levels. The allocation of interrupt sources between on-chip peripherals and external inputs pins varies according to the specific ...
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External Interrupts The /INT0 and /INT1 external interrupt sources are configurable as active high or low, edge or level sensi- tive. The IN0PL (/INT0 Polarity) and IN1PL (/INT1 Polarity) bits in the IT01CF register select active high or active ...
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C8051F310/1/2/3/4/5 Table 8.4. Interrupt Summary Interrupt Interrupt Source Vector Reset 0x0000 External Interrupt 0 (/INT0) 0x0003 Timer 0 Overflow 0x000B External Interrupt 1 (/INT1) 0x0013 Timer 1 Overflow 0x001B UART0 0x0023 Timer 2 Overflow 0x002B SPI0 0x0033 SMB0 0x003B RESERVED ...
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Interrupt Register Descriptions The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the ...
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C8051F310/1/2/3/4/5 SFR Definition 8.8. IP: Interrupt Priority R/W R/W R/W - PSPI0 PT2 Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 1, Write = don't care. Bit6: PSPI0: Serial Peripheral Interface (SPI0) Interrupt Priority Control. This bit sets the priority of ...
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SFR Definition 8.9. EIE1: Extended Interrupt Enable 1 R/W R/W R/W ET3 ECP1 ECP0 Bit7 Bit6 Bit5 Bit7: ET3: Enable Timer 3 Interrupt. This bit sets the masking of the Timer 3 interrupt. 0: Disable Timer 3 interrupts. 1: Enable ...
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C8051F310/1/2/3/4/5 SFR Definition 8.10. EIP1: Extended Interrupt Priority 1 R/W R/W R/W PT3 PCP1 PCP0F Bit7 Bit6 Bit5 Bit7: PT3: Timer 3 Interrupt Priority Control. This bit sets the priority of the Timer 3 interrupt. 0: Timer 3 interrupts set ...
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SFR Definition 8.11. IT01CF: INT0/INT1 Configuration R/W R/W R/W IN1PL IN1SL2 IN1SL1 Bit7 Bit6 Bit5 Note: Refer to Figure 17.1 for INT0/1 edge- or level-sensitive interrupt selection. Bit7: IN1PL: /INT1 Polarity 0: /INT1 input is active low. 1: /INT1 input ...
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C8051F310/1/2/3/4/5 8.4. Power Management Modes The CIP-51 core has two software programmable power management modes: Idle and Stop. Idle mode halts the CPU while leaving the peripherals and clocks active. In Stop mode, the CPU is halted, all inter- rupts ...
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Stop Mode Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc- tion that sets the bit completes execution. In Stop mode the internal oscillator, CPU, and all digital peripher- ...
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C8051F310/1/2/3/4/5 96 Notes Rev. 1.5 ...
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Reset Sources Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur: • CIP-51 halts program execution • Special Function Registers (SFRs) are initialized to their ...
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C8051F310/1/2/3/4/5 9.1. Power-On Reset During power-up, the device is held in a reset state and the RST pin is driven low until additional delay occurs before the device is released from reset; the delay decreases as ...
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Power-Fail Reset / V DD When a power-down transition or power irregularity causes V monitor will drive the RST pin low and hold the CIP- reset state (see Figure 9.2). When level above V ...
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C8051F310/1/2/3/4/5 9.3. External Reset The external RST pin provides a means for external circuitry to force the device into a reset state. Assert- ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of ...
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Software Reset Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol- lowing a software forced reset. The state of the RST pin is unaffected by this reset. ...
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C8051F310/1/2/3/4/5 Table 9.1. Reset Electrical Characteristics –40 to +85 °C unless otherwise specified. Parameter I RST Output Low Voltage OL RST Input High Voltage RST Input Low Voltage RST Input Pullup Current RST = 0 Monitor Threshold (V ...
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Flash Memory On-chip, re-programmable Flash memory is included for program code and non-volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the C2 interface or by soft- ware using the MOVX ...
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C8051F310/1/2/3/4/5 10.1.3. Flash Write Procedure Flash bytes are programmed by software with the following sequence: Step 1. Disable interrupts (recommended). Step 2. Erase the 512-byte Flash page containing the target location, as described in 10.1.2. Step 3. Set the PSWE ...
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Non-volatile Data Storage The Flash memory can be used for non-volatile data storage as well as program code. This allows data such as calibration coefficients to be calculated and stored at run time. Data is written using the MOVX ...
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C8051F310/1/2/3/4/5 Accessing Flash from the C2 debug interface: 1. Any unlocked page may be read, written, or erased. 2. Locked pages cannot be read, written, or erased. 3. The page containing the Lock Byte may be read, written, or erased ...
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SFR Definition 10.1. PSCTL: Program Store R/W Control R/W R/W R Bit7 Bit6 Bit5 Bits7-2: UNUSED: Read = 000000b, Write = don’t care. Bit1: PSEE: Program Store Erase Enable Setting this bit (in combination with PSWE) allows ...
Page 108
C8051F310/1/2/3/4/5 SFR Definition 10.3. FLSCL: Flash Scale R/W R/W R/W FOSE Reserved Reserved Reserved Reserved Reserved Reserved Reserved 10000000 Bit7 Bit6 Bit5 Bits7: FOSE: Flash One-shot Enable This bit enables the Flash read one-shot. When the Flash one-shot disabled, the ...
Page 109
External RAM The C8051F31x devices include 1024 bytes of RAM mapped into the external data memory space. All of these address locations may be accessed using the external move instruction (MOVX) and the data pointer (DPTR), or using MOVX ...
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C8051F310/1/2/3/4/5 110 Notes Rev. 1.5 ...
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Oscillators C8051F31x devices include a programmable internal oscillator and an external oscillator drive circuit. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as shown in Figure 12.1. The system clock can be sourced ...
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C8051F310/1/2/3/4/5 SFR Definition 12.1. OSCICL: Internal Oscillator Calibration R/W R/W R/W Bit7 Bit6 Bit5 Bit7: UNUSED. Read = 0. Write = don’t care. Bits 6-0: OSCICL: Internal Oscillator Calibration Register. This register determines the internal oscillator period. This reset value ...
Page 113
SFR Definition 12.3. CLKSEL: Clock Select R/W R/W R/W Reserved Reserved Reserved Reserved Reserved Reserved Reserved CLKSL0 00000000 Bit7 Bit6 Bit5 Bits7-1: Reserved. Read = 0000000b, Must Write = 0000000. Bit0: CLKSL0: System Clock Source Select Bit. 0: SYSCLK derived ...
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C8051F310/1/2/3/4/5 12.2. External Oscillator Drive Circuit The external oscillator circuit may drive an external crystal, ceramic resonator, capacitor network. A CMOS clock may also provide a clock input. For a crystal or ceramic resonator configuration, the crys- tal/resonator ...
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SFR Definition 12.4. OSCXCN: External Oscillator Control R R/W R/W XTLVLD XOSCMD2 XOSCMD1 XOSCMD0 Bit7 Bit6 Bit5 Bit7: XTLVLD: Crystal Oscillator Valid Flag. (Read only when XOSCMD = 11x.) 0: Crystal Oscillator is unused or not yet stable. 1: Crystal ...
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C8051F310/1/2/3/4/5 12.4. External Crystal Example If a crystal or ceramic resonator is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 12.1, Option 1. The External Oscillator Frequency Control value (XFCN) ...
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External RC Example network is used as an external oscillator source for the MCU, the circuit should be configured as shown in Figure 12.1, Option 2. The capacitor should be no greater than 100 pF; however, ...
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C8051F310/1/2/3/4/5 118 Notes Rev. 1.5 ...
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... Digital and analog resources are available through 29 I/O pins (C8051F310/2/ I/O pins (C8051F311/3/5). Port pins are organized as three byte-wide Ports and one 5-bit (C8051F310/2/4) or 1-bit (C8051F311/3/5) Port. Each of the Port pins can be defined as general-purpose I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as shown in Figure 13.3. ...
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C8051F310/1/2/3/4/5 /WEAK-PULLUP PUSH-PULL /PORT-OUTENABLE PORT-OUTPUT ANALOG INPUT PORT-INPUT Figure 13.2. Port I/O Cell Block Diagram 120 VDD GND Analog Select Rev. 1.5 VDD (WEAK) PORT PAD ...
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Priority Crossbar Decoder The Priority Crossbar Decoder (Figure 13.3) assigns a priority to each I/O function, starting at the top with UART0. When a digital resource is selected, the least-significant unassigned Port pin is assigned to that resource (excluding ...
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C8051F310/1/2/3/4 Signals PIN I TX0 RX0 SCK MISO MOSI NSS† SDA SCL CP0 CP0A CP1 CP1A SYSCLK CEX0 CEX1 CEX2 CEX3 CEX4 ECI P0SKIP[0:7] ...
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Port I/O Initialization Port I/O initialization consists of the following steps: Step 1. Select the input mode (analog or digital) for all Port pins, using the Port Input Mode register (PnMDIN). Step 2. Select the output mode (open-drain or ...
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C8051F310/1/2/3/4/5 SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0 R/W R/W R/W CP1AE CP1E CP0AE Bit7 Bit6 Bit5 Bit7: CP1AE: Comparator1 Asynchronous Output Enable 0: Asynchronous CP1 unavailable at Port pin. 1: Asynchronous CP1 routed to Port pin. Bit6: ...
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SFR Definition 13.2. XBR1: Port I/O Crossbar Register 1 R/W R/W R/W WEAKPUD XBARE T1E Bit7 Bit6 Bit5 Bit7: WEAKPUD: Port I/O Weak Pullup Disable. 0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input). 1: ...
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C8051F310/1/2/3/4/5 13.3. General Purpose Port I/O Port pins that remain unassigned by the Crossbar and are not used by analog peripherals can be used for general purpose I/O. Ports3-0 are accessed through corresponding special function registers (SFRs) that are both ...
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SFR Definition 13.5. P0MDOUT: Port0 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P0.7-P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n ...
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C8051F310/1/2/3/4/5 SFR Definition 13.7. P1: Port1 R/W R/W R/W P1.7 P1.6 P1.5 Bit7 Bit6 Bit5 Bits7-0: P1.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P1MDOUT.n ...
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SFR Definition 13.9. P1MDOUT: Port1 Output Mode R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: Output Configuration Bits for P1.7-P1.0 (respectively): ignored if corresponding bit in regis- ter P1MDIN is logic 0. 0: Corresponding P1.n Output is open-drain. 1: Corresponding P1.n ...
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C8051F310/1/2/3/4/5 SFR Definition 13.11. P2: Port2 R/W R/W R/W P2.7 P2.6 P2.5 Bit7 Bit6 Bit5 Bits7-0: P2.[7:0] Write - Output appears on I/O pins per Crossbar Registers. 0: Logic Low Output. 1: Logic High Output (high impedance if corresponding P2MDOUT.n ...
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... Read - Always reads ‘1’ if selected as analog input in register P3MDIN. Directly reads Port pin when configured as digital input. 0: P3.n pin is logic low. 1: P3.n pin is logic high. Note: Only P3.0-P3.4 are associated with Port pins on C8051F10/2/4 devices; Only P3.0 is associated with a Port pin on C8051F311/3/5 devices. C8051F310/1/2/3/4/5 R/W R/W R/W ...
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... Output Configuration Bits for P3.4-P3.0 (respectively): ignored if corresponding bit in regis- ter P3MDIN is logic 0. 0: Corresponding P3.n Output is open-drain. 1: Corresponding P3.n Output is push-pull. Note: Only P3.0-P3.4 are associated with Port pins on C8051F10/2/4 devices; Only P3.0 is associated with a Port pin on C8051F311/3/5 devices. 132 R/W R/W R/W ...
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Table 13.1. Port I/O DC Electrical Characteristics V = 2.7 to 3.6 V, –40 to +85 °C unless otherwise specified DD Parameters mA, Port I/O push-pull -10 µA, Port I/O push-pull Output High Voltage ...
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C8051F310/1/2/3/4/5 134 Notes Rev. 1.5 ...
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SMBus The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to the interface by the system ...
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C8051F310/1/2/3/4/5 14.1. Supporting Documents It is assumed the reader is familiar with or has access to the following supporting documents: • The I2C-Bus and How to Use It (including specifications), Philips Semiconductor. • The I2C-Bus Specification—Version 2.0, Philips Semiconductor. • ...
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SMBus Operation Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ). The master device initiates both ...
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C8051F310/1/2/3/4/5 14.3.2. Clock Low Extension SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow slower slave ...
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Using the SMBus The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con- trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides the following application-independent ...
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C8051F310/1/2/3/4/5 14.4.1. SMBus Configuration Register The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes, select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is set, the ...
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Figure 14.4 shows the typical SCL generation described by Equation 14.2. Notice that T twice as large The actual SCL output may vary due to other devices on the bus (SCL may be LOW extended low by ...
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C8051F310/1/2/3/4/5 SFR Definition 14.1. SMB0CF: SMBus Clock/Configuration R/W R/W R ENSMB INH BUSY Bit7 Bit6 Bit5 Bit7: ENSMB: SMBus Enable. This bit enables/disables the SMBus interface. When enabled, the interface constantly mon- itors the SDA and SCL pins. 0: SMBus ...
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SMB0CN Control Register SMB0CN is used to control the interface and to provide status information (see SFR Definition 14.2). The higher four bits of SMB0CN (MASTER, TXMODE, STA, and STO) form a status vector that can be used to ...
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C8051F310/1/2/3/4/5 SFR Definition 14.2. SMB0CN: SMBus Control R R R/W MASTER TXMODE STA Bit7 Bit6 Bit5 Bit7: MASTER: SMBus Master/Slave Indicator. This read-only bit indicates when the SMBus is operating as a master. 0: SMBus operating in Slave Mode. 1: ...
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Table 14.3. Sources for Hardware Changes to SMB0CN Bit Set by Hardware When... • A START is generated. MASTER • START is generated. • SMB0DAT is written before the start of an TXMODE SMBus frame. • A START followed by ...
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C8051F310/1/2/3/4/5 14.4.3. Data Register The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been received. Software may safely read or write to the data register when the SI flag is ...
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SMBus Transfer Modes The SMBus interface may be configured to operate as master and/or slave. At any particular time, it will be operating in one of the following four modes: Master Transmitter, Master Receiver, Slave Transmitter, or Slave Receiver. ...
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C8051F310/1/2/3/4/5 14.5.2. Master Receiver Mode Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the START condition and transmits the first byte containing the address of the target slave and the ...
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Slave Receiver Mode Serial data is received on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode when a START followed by a slave address and ...
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C8051F310/1/2/3/4/5 14.5.4. Slave Transmitter Mode Serial data is transmitted on SDA and the clock is received on SCL. When slave events are enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START ...
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SMBus Status Decoding The current SMBus status can be easily decoded using the SMB0CN register. In the table below, STATUS VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. Note that the shown response ...
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C8051F310/1/2/3/4/5 Table 14.4. SMBus Status Decoding (Continued) Values Read Current SMbus State A slave byte was transmitted NACK received. A slave byte was transmitted; 0100 ACK received. A Slave byte was transmitted ...
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UART0 UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details in Section “15.1. ...
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C8051F310/1/2/3/4/5 15.1. Enhanced Baud Rate Generation The UART0 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer ...
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Operational Modes UART0 provides standard asynchronous, full duplex communication. The UART mode (8-bit or 9-bit) is selected by the S0MODE bit (SCON0.7). Typical UART connection options are shown in Figure 15.3. Figure 15.3. UART Interconnect Diagram 15.2.1. 8-Bit UART ...
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C8051F310/1/2/3/4/5 15.2.2. 9-Bit UART 9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma- ble ninth data bit, and a stop bit. The state of the ninth transmit ...
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Multiprocessor Communications 9-Bit UART mode supports multiprocessor communication between a master processor and one or more slave processors by special use of the ninth data bit. When a master processor wants to transmit to one or more slaves, it ...
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C8051F310/1/2/3/4/5 SFR Definition 15.1. SCON0: Serial Port 0 Control R/W R R/W S0MODE MCE0 Bit7 Bit6 Bit5 Bit7: S0MODE: Serial Port 0 Operation Mode. This bit selects the UART0 Operation Mode. 0: 8-bit UART with Variable Baud Rate. 1: 9-bit ...
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SFR Definition 15.2. SBUF0: Serial (UART0) Port Data Buffer R/W R/W R/W Bit7 Bit6 Bit5 Bits7-0: SBUF0[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB) This SFR accesses two registers; a transmit shift register and a receive latch register. When data is ...
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C8051F310/1/2/3/4/5 Table 15.1. Timer Settings for Standard Baud Rates Using the Internal Oscillator Target Baud Rate Baud Rate % Error (bps) 230400 –0.32% 115200 –0.32% 57600 0.15% 28800 –0.32% 14400 0.15% 9600 –0.32% 2400 –0.32% 1200 0.15% † SCA1-SCA0 and ...
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Table 15.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% 115200 ...
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C8051F310/1/2/3/4/5 Table 15.5. Timer Settings for Standard Baud Rates Using an External 11.0592 MHz Target Baud Rate Baud Rate % Error (bps) 230400 0.00% 115200 0.00% 57600 0.00% 28800 0.00% 14400 0.00% 9600 0.00% 2400 0.00% 1200 0.00% 230400 0.00% ...
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Enhanced Serial Peripheral Interface (SPI0) The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul- tiple ...
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C8051F310/1/2/3/4/5 16.1. Signal Descriptions The four signals used by SPI0 (MOSI, MISO, SCK, NSS) are described below. 16.1.1. Master Out, Slave In (MOSI) The master-out, slave-in (MOSI) signal is an output from a master device and an input to slave ...
Page 165
SPI0 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus. SPI0 is placed in master mode by setting the Master Enable flag (MSTEN, SPI0CN.6). Writing a byte of data to the SPI0 data ...
Page 166
C8051F310/1/2/3/4/5 Master Device 1 Figure 16.2. Multiple-Master Mode Connection Diagram Master Device Figure 16.3. 3-Wire Single Master and Slave Mode Connection Diagram Master Device GPIO Figure 16.4. 4-Wire Single Master and Slave Mode Connection Diagram 166 NSS GPIO MISO MISO ...
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SPI0 Slave Mode Operation When SPI0 is enabled and not configured as a master, it will operate as a SPI slave slave, bytes are shifted in through the MOSI pin and out through the MISO pin by ...
Page 168
C8051F310/1/2/3/4/5 16.5. Serial Clock Timing Four combinations of serial clock phase and polarity can be selected using the clock control bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.5) selects one of two clock phases (edge used to ...
Page 169
SCK (CKPOL=0, CKPHA=0) SCK (CKPOL=1, CKPHA=0) MOSI MSB Bit 6 MISO MSB Bit 6 NSS (4-Wire Mode) Figure 16.6. Slave Mode Data/Clock Timing (CKPHA = 0) SCK (CKPOL=0, CKPHA=1) SCK (CKPOL=1, CKPHA=1) MOSI MSB MISO MSB NSS (4-Wire Mode) Figure ...
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C8051F310/1/2/3/4/5 16.6. SPI Special Function Registers SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special function registers related ...
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SFR Definition 16.2. SPI0CN: SPI0 Control R/W R/W R/W SPIF WCOL MODF RXOVRN NSSMD1 NSSMD0 Bit7 Bit6 Bit5 Bit 7: SPIF: SPI0 Interrupt Flag. This bit is set to logic 1 by hardware at the end of a data transfer. ...
Page 172
C8051F310/1/2/3/4/5 SFR Definition 16.3. SPI0CKR: SPI0 Clock Rate R/W R/W R/W SCR7 SCR6 SCR5 Bit7 Bit6 Bit5 Bits 7-0: SCR7-SCR0: SPI0 Clock Rate. These bits determine the frequency of the SCK output when the SPI0 module is configured for master ...
Page 173
SCK* T MCKH MISO MOSI * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.8. SPI Master Timing (CKPHA = 0) SCK* T MCKH T MIS MISO MOSI * SCK is ...
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C8051F310/1/2/3/4/5 NSS T SE SCK* T CKH MOSI T SEZ MISO * SCK is shown for CKPOL = 0. SCK is the opposite polarity for CKPOL = 1. Figure 16.10. SPI Slave Timing (CKPHA = 0) NSS T SE SCK* ...
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Table 16.1. SPI Slave Timing Parameters Parameter Description † Master Mode Timing (See Figure 16.8 and Figure 16.9) T SCK High Time MCKH T SCK Low Time MCKL T MISO Valid to SCK Shift Edge MIS T SCK Shift Edge ...
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C8051F310/1/2/3/4/5 176 Notes Rev. 1.5 ...
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Timers Each MCU includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the ADC, SMBus, or for general purpose use. These timers can be ...
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C8051F310/1/2/3/4/5 The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to “13.1. Priority Crossbar Decoder” on page 121 ...
Page 179
Mode 1: 16-bit Counter/Timer Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0. ...
Page 180
C8051F310/1/2/3/4/5 17.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) In Mode 3, Timer 0 is configured as two separate 8-bit counter/timers held in TL0 and TH0. The counter/timer in TL0 is controlled using the Timer 0 control/status bits in ...
Page 181
SFR Definition 17.1. TCON: Timer Control R/W R/W R/W TF1 TR1 TF0 Bit7 Bit6 Bit5 Bit7: TF1: Timer 1 Overflow Flag. Set by hardware when Timer 1 overflows. This flag can be cleared by software but is auto- matically cleared ...
Page 182
C8051F310/1/2/3/4/5 SFR Definition 17.2. TMOD: Timer Mode R/W R/W R/W GATE1 C/T1 T1M1 Bit7 Bit6 Bit5 Bit7: GATE1: Timer 1 Gate Control. 0: Timer 1 enabled when TR1 = 1 irrespective of /INT1 logic level. 1: Timer 1 enabled only ...
Page 183
SFR Definition 17.3. CKCON: Clock Control R/W R/W R/W T3MH T3ML T2MH Bit7 Bit6 Bit5 Bit7: T3MH: Timer 3 High Byte Clock Select. This bit selects the clock supplied to the Timer 3 high byte if Timer 3 is configured ...
Page 184
C8051F310/1/2/3/4/5 SFR Definition 17.4. TL0: Timer 0 Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TL0: Timer 0 Low Byte. The TL0 register is the low byte of the 16-bit Timer 0. SFR Definition 17.5. TL1: Timer 1 ...
Page 185
Timer 2 Timer 16-bit timer formed by two 8-bit SFRs: TMR2L (low byte) and TMR2H (high byte). Timer 2 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T2SPLIT bit (TMR2CN.3) defines the ...
Page 186
C8051F310/1/2/3/4/5 17.2.2. 8-bit Timers with Auto-Reload When T2SPLIT is set, Timer 2 operates as two 8-bit timers (TMR2H and TMR2L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR2RLL holds the reload value for TMR2L; ...
Page 187
SFR Definition 17.8. TMR2CN: Timer 2 Control R/W R/W R/W TF2H TF2L TF2LEN Bit7 Bit6 Bit5 Bit7: TF2H: Timer 2 High Byte Overflow Flag. Set by hardware when the Timer 2 high byte overflows from 0xFF to 0x00 ...
Page 188
C8051F310/1/2/3/4/5 SFR Definition 17.9. TMR2RLL: Timer 2 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR2RLL: Timer 2 Reload Register Low Byte. TMR2RLL holds the low byte of the reload value for Timer 2. SFR Definition ...
Page 189
Timer 3 Timer 16-bit timer formed by two 8-bit SFRs: TMR3L (low byte) and TMR3H (high byte). Timer 3 may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The T3SPLIT bit (TMR3CN.3) defines the ...
Page 190
C8051F310/1/2/3/4/5 17.3.2. 8-bit Timers with Auto-Reload When T3SPLIT is set, Timer 3 operates as two 8-bit timers (TMR3H and TMR3L). Both 8-bit timers oper- ate in auto-reload mode as shown in Figure 17.5. TMR3RLL holds the reload value for TMR3L; ...
Page 191
SFR Definition 17.13. TMR3CN: Timer 3 Control R/W R/W R/W TF3H TF3L TF3LEN Bit7 Bit6 Bit5 Bit7: TF3H: Timer 3 High Byte Overflow Flag. Set by hardware when the Timer 3 high byte overflows from 0xFF to 0x00 ...
Page 192
C8051F310/1/2/3/4/5 SFR Definition 17.14. TMR3RLL: Timer 3 Reload Register Low Byte R/W R/W R/W Bit7 Bit6 Bit5 Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte. TMR3RLL holds the low byte of the reload value for Timer 3. SFR Definition ...
Page 193
Programmable Counter Array The Programmable Counter Array (PCA0) provides enhanced timer functionality while requiring less CPU intervention than the standard 8051 counter/timers. The PCA consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. Each capture/compare module has ...
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C8051F310/1/2/3/4/5 18.1. PCA Counter/Timer The 16-bit PCA counter/timer consists of two 8-bit SFRs: PCA0L and PCA0H. PCA0H is the high byte (MSB) of the 16-bit counter/timer and PCA0L is the low byte (LSB). Reading PCA0L automatically latches the value of ...
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Capture/Compare Modules Each module can be configured to operate independently in one of six operation modes: Edge-triggered Capture, Software Timer, High Speed Output, Frequency Output, 8-Bit Pulse Width Modulator, or 16-Bit Pulse Width Modulator. Each module has Special Function ...
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C8051F310/1/2/3/4/5 18.2.1. Edge-triggered Capture Mode In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA counter/ timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and PCA0CPHn). ...
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Software Timer (Compare) Mode In Software Timer mode, the PCA counter/timer value is compared to the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1 and ...
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C8051F310/1/2/3/4/5 18.2.3. High-Speed Output Mode In High Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and PCA0CPLn) Setting the TOGn, MATn, and ...
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Frequency Output Mode Frequency Output Mode produces a programmable-frequency square wave on the module’s associated CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out- put is toggled. The frequency of ...
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C8051F310/1/2/3/4/5 18.2.5. 8-Bit Pulse Width Modulator Mode Each module can be used independently to generate a pulse width modulated (PWM) output on its associ- ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA ...