C8051F986-GU Silicon Laboratories Inc, C8051F986-GU Datasheet - Page 219
C8051F986-GU
Manufacturer Part Number
C8051F986-GU
Description
IC MCU 8BIT 8KB FLASH 24QSOP
Manufacturer
Silicon Laboratories Inc
Series
C8051F9xxr
Specifications of C8051F986-GU
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
24-QSOP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F9x
Core
8051
Data Ram Size
512 B
Interface Type
I2C, SMBus, Enhanced UART, Enhanced SPI
Maximum Clock Frequency
7 KHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
2.4 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F996DK
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit, 10 Channel
On-chip Dac
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1953-5
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Manufacturer
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Part Number:
C8051F986-GU
Manufacturer:
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Quantity:
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Registers XBR0, XBR1, and XBR2 are used to assign the digital I/O resources to the physical I/O Port
pins. Note that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus
(SDA and SCL); when either UART is selected, the Crossbar assigns both pins associated with the UART
(TX and RX). UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned
to P0.4; UART RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized
functions have been assigned.
Notes:
1. The Crossbar must be enabled (XBARE = 1) before any Port pin is used as a digital output. Port output drivers
2. When SMBus is selected in the Crossbar, the pins associated with SDA and SCL will automatically be forced
3. SPI0 can be operated in either 3-wire or 4-wire modes, depending on the state of the NSSMD1-NSSMD0 bits in
4. For given XBRn, PnSKIP, and SPInCN register settings, one can determine the I/O pin-out of the device using
5. On 20-pin devices, P1.4 should be skipped in the Crossbar. It is not available as a device pin.
are disabled while the Crossbar is disabled.
into open-drain output mode regardless of the PnMDOUT setting.
register SPI0CN. The NSS signal is only routed to a Port pin when 4-wire mode is selected. When SPI0 is
selected in the Crossbar, the SPI0 mode (3-wire or 4-wire) will affect the pinout of all digital functions lower in
priority than SPI0.
Figure 21.3.
Rev. 1.0
C8051F99x-C8051F98x
219
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