MC9S08SH4CTJ Freescale Semiconductor, MC9S08SH4CTJ Datasheet - Page 312
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MC9S08SH4CTJ
Manufacturer Part Number
MC9S08SH4CTJ
Description
IC MCU 8BIT 4K FLASH 20-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08SH4CTJ.pdf
(338 pages)
Specifications of MC9S08SH4CTJ
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
17
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
S08SH
Core
HCS08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
17
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO, DEMO9S08SH32, DEMO9S08SH8
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
A/d Bit Size
10 bit
A/d Channels Available
12
Height
1.05 mm
Length
6.6 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4.5 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S08SH4CTJR
Manufacturer:
FREESCALE
Quantity:
20 000
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Appendix A Electrical Characteristics
A.12.3
Table A-15
312
1
2
3
4
5
and
SPI
Num
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
Refer to
All timing is shown with respect to 20% V
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
Time to data active from high-impedance state.
Hold time to high-impedance state.
10
11
12
1
2
3
4
5
6
7
8
9
Figure A-14
1
Figure A-14
D
D
D
D
D
D
D
D
D
D
D
D
C
Cycle time
Enable lead time
Enable lag time
Clock (SPSCK) high time
Clock (SPSCK) low time
Data setup time (inputs)
Data hold time (inputs)
Access time, slave
Disable time, slave
Data setup time (outputs)
Data hold time (outputs)
Operating frequency
through
through
Table A-15. SPI Electrical Characteristic
MC9S08SH8 MCU Series Data Sheet, Rev. 3
Rating
Figure A-17
Master and Slave
Master and Slave
Figure
3
4
2
A-17.
Master
Master
Master
Master
Master
Master
Master
Master
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
DD
describe the timing requirements for the SPI system.
and 70% V
Symbol
t
t
t
t
t
t
t
t
SCKH
SCKL
t
t
SI(M)
HI(M)
t
t
SI(S)
HI(S)
Lead
Lead
t
t
t
t
t
SCK
SCK
Lag
Lag
f
f
SO
SO
HO
HO
t
dis
op
op
A
DD
, unless noted; 100 pF load on all SPI
1/2 t
1/2 t
f
Bus
SCK
SCK
–10
–10
Min
1/2
1/2
30
30
30
30
25
25
dc
—
—
—
/2048
2
4
0
– 25
– 25
f
2048
Bus
Max
1/2
1/2
—
—
—
—
—
—
—
—
—
40
40
—
—
—
—
5
5
/4
Freescale Semiconductor
t
t
t
t
MHz
Unit
SCK
SCK
SCK
SCK
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cyc
cyc
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