STM32F105RBT6 STMicroelectronics, STM32F105RBT6 Datasheet - Page 16
![MCU ARM 128KB FLASH MEM 64-LQFP](/photos/12/15/121547/stm32f105rbt6_sml.jpg)
STM32F105RBT6
Manufacturer Part Number
STM32F105RBT6
Description
MCU ARM 128KB FLASH MEM 64-LQFP
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F105V8T6.pdf
(101 pages)
Specifications of STM32F105RBT6
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
72MHz
Connectivity
CAN, Ethernet, I²C, IrDA, LIN, SPI, UART/USART, USB OTG
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
51
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
STM32F105x
Core
ARM Cortex M3
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, I2C, SPI, USART
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
51
Number Of Timers
10
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit x 2, 16 Channel
On-chip Dac
12 bit x 2, 2 Channel
For Use With
497-10591 - DAUGHTER BOARD FOR STM32497-9040 - DEV KIT FOR STM32497-9041 - DEV KIT FOR STM32497-9042 - DEV KIT FOR STM32497-9043 - DEV KIT FOR STM32497-8924 - EVAL BOARD FOR STM32F107VCT497-8853 - BOARD DEMO STM32 UNIV USB-UUSCI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-8920
Available stocks
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Quantity
Price
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Description
Note:
2.3.13
2.3.14
16/101
●
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 12-channel general-purpose DMAs (7 channels for DMA1 and 5 channels for
DMA2) are able to manage memory-to-memory, peripheral-to-memory and memory-to-
peripheral transfers. The two DMA controllers support circular buffer management,
removing the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I
and advanced control timers TIMx, DAC, I
In the STM32F107xx, there is a DMA controller dedicated for use with the Ethernet (see
Section 2.3.20: Ethernet MAC interface with dedicated DMA and IEEE 1588 support
more information).
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
V
registers used to store 84 bytes of user application data when V
They are not reset by a system or power reset, and they are not reset when the device
wakes up from the Standby mode.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low-speed RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural quartz deviation. The RTC features
a 32-bit programmable counter for long term measurement using the Compare register to
generate an alarm. A 20-bit prescaler is used for the time base clock and is by default
configured to generate a time base of 1 second from a clock at 32.768 kHz.
For more information, please refer to AN2604: “STM32F101xx and STM32F103xx RTC
calibration”, available from www.st.com.
DD
supply when present or through the V
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and register contents are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Doc ID 15274 Rev 5
2
BAT
S and ADC.
pin. The backup registers are forty-two 16-bit
2
C, USART, general-purpose, basic
STM32F105xx, STM32F107xx
DD
power is not present.
for