Z16F2810FI20SG Zilog, Z16F2810FI20SG Datasheet - Page 148
Z16F2810FI20SG
Manufacturer Part Number
Z16F2810FI20SG
Description
IC ZNEO MCU FLASH 128K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F2810FI20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F2x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
4 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4567
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F2810FI20SG
Manufacturer:
Zilog
Quantity:
211
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Table 78. PWM Output Control Register (PWMOUT)
.
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[5:0]
IN2L/IN2H/
IN1L/IN1H/
IN0L/IN0H
Bit Position
[7,6]
Reserved
[5, 3, 1]
OUT2L/
OUT1L/
OUT0L
[4, 2, 0]
OUT2H/
OUT1H/
OUT0H
PWM Output Control Register
Current-Sense Sample and Hold Control Registers
Reserved Reserved
R
7
0
Value (H)
Value (H) Description
The PWM output control (PWMOUT) register enables modulator control of the six PWM
output signals. Output control is enabled by the OUTCTL bit in the PWMCTL0 register.
The PWM continues to operate but has no effect on the disabled PWM pins. If a fault
condition is detected, all PWM outputs are forced to their selected off state.
The current-sense sample/hold control register defines the behavior of the dedicated
current sense sample and hold inputs to the ADC from the operational amplifier. These
input hold the current input value whenever all high-side outputs or all low-side outputs
are in the on-state. The register bits control which PWM outputs must be asserted to
0
1
0
1
0
1
R
6
0
Sample PWM pins
A Low-level signal was read on the pins.
A High-level signal was read on the pins.
Description
Must be 0.
PWM 2L/1L/0L output configuration
PWM 2L/1L/0L output signal is enabled and controlled by PWM.
PWM 2L/1L/0L output signal is in low-side off-state.
PWM 2H/1H/0H output configuration
PWM 2H/1H/0H output signal is enabled and controlled by PWM.
PWM 2H/1H/0H output signal is in high-side off-state.
OUT2L
R/W
5
0
P R E L I M I N A R Y
OUT2H
R/W
4
0
FF_E387H
OUT1L
R/W
3
0
OUT1H
R/W
2
0
Multi-Channel PWM Timer
Product Specification
ZNEO
OUT0L
R/W
1
0
Z16F Series
OUT0H
R/W
0
0
133
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