Z16F2810AG20SG Zilog, Z16F2810AG20SG Datasheet - Page 126

• Manufacturer Part Number: Z16F2810AG20SG
• Description: IC ZNEO MCU FLASH 128K 64LQFP
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810AG20SG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Processor Series: Z16F2x
• Core: Zneo
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z16F2800100ZCOG
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4535

PS022008-0810
Bit Position
[6]
TPOL
Value (H) Description
Timer Input/Output Polarity
This bit is a fu nction of the cur rent operating mode of the timer. It
determines the polarity of the input and/or output signal. When the timer is
disabled, the timer output signal is set to the value of this bit.
ONE-SHOT mode —If the timer is enabled, the timer output signal pulses
(changes state) for one system clock cycle after timer Reload.
CONTINUOUS mode—If the timer is enabled, the timer output signal is
complemented after timer Reload.
COUNTER mode—If the timer is enabled, the timer output signal is
complemented after timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM SINGLE OUTPUT mode—When enabled, the timer output is forced
to TPOL after PWM count match and forced back to TPOL after Reload.
CAPTURE mode—If the timer is enabled, the timer output signal is
complemented after timer Reload.
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARE mode—The timer output signal is complemented after timer
Reload.
GATED mode—The timer output signal is complemented after timer
Reload.
0 = Timer counts when the timer input signal is High and interrupts are
generated on the falling edge of the timer input.
1 = Timer counts when the timer input signal is Low and interrupts are
generated on the rising edge of the timer input.
CAPTURE/COMPARE mode—If the timer is enabled, the timer output
signal is complemented after timer Reload.
0 = Counting starts on the first rising edge of the timer Input signal. 
The current count is captured on subsequent rising edges of the timer 
input signal.
1 = Counting starts on the first falling edge of the timer input signal. 
The current count is captured on subsequent falling edges of the timer
input signal.
P R E L I M I N A R Y
Product Specification
ZNEO
Z16F Series
Timers
111