Z16F3211FI20SG Zilog, Z16F3211FI20SG Datasheet - Page 190
Z16F3211FI20SG
Manufacturer Part Number
Z16F3211FI20SG
Description
IC ZNEO MCU FLASH 32K 80QFP
Manufacturer
Zilog
Series
Encore!® ZNEOr
Datasheet
1.Z16F2800100ZCOG.pdf
(388 pages)
Specifications of Z16F3211FI20SG
Core Processor
ZNEO
Core Size
16-Bit
Speed
20MHz
Connectivity
EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
60
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
80-BQFP
Processor Series
Z16F3x
Core
Zneo
Data Bus Width
16 bit
Data Ram Size
2 B
Interface Type
ESPI, I2C, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
60
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
Z16F2800100ZCOG
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4569
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
Z16F3211FI20SG
Manufacturer:
Zilog
Quantity:
131
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Infrared Encoder/Decoder Control Register Definitions
PS022008-0810
Caution:
this process is repeated. If the incoming data is a logical 1 (no pulse), the Endec returns to
the initial state and waits for the next falling edge. As each falling edge is detected, the
Endec clock counter is reset, resynchronizing the Endec to the incoming signal. This
allows the Endec to tolerate jitter and baud rate errors in the incoming data stream.
Resynchronizing the Endec does not alter the operation of the UART, which ultimately
receives the data. The UART is only synchronized to the incoming data stream when a
Start bit is received.
All Infrared Endec configuration and status information is set by the UART control
registers as defined in the beginning in
on page 152.
To prevent spurious signals during IrDA data transmission, set the IREN bit in the UARTx
Control 1 register to 1 to enable the Infrared Encoder/Decoder before enabling the GPIO
port alternate function for the corresponding pin.
P R E L I M I N A R Y
LIN-UART Control Register Definitions
Infrared Encoder/Decoder
Product Specification
ZNEO
Z16F Series
174
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