EZ80F93AZ020SG Zilog, EZ80F93AZ020SG Datasheet - Page 90
![IC ACCLAIM MCU 64KB 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80F93AZ020SG
Manufacturer Part Number
EZ80F93AZ020SG
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
100-LQFP
Processor Series
EZ80F93x
Core
eZ80
Data Bus Width
8 bit
Data Ram Size
4 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
24
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
eZ80F920200ZCOG
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
269-3874
EZ80F93AZ020SG
EZ80F93AZ020SG
Available stocks
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Part Number
Manufacturer
Quantity
Price
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PS015313-0508
Note:
Note:
Timer Data Register—Low Byte
This Read Only register returns the Low byte of the current count value of the selected
timer. The Timer Data Register—Low Byte, listed in
is in operation. Reading the current count value does not affect timer operation. To read
the 16-bit data of the current count value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}, first
read the Timer Data Register—Low Byte and then read the Timer Data Register—High
Byte. The Timer Data Register—High Byte value is latched when a Read of the Timer
Data Register—Low Byte occurs.
Table 33. Timer Data Register—Low Byte(TMR0_DR_L = 0081h, TMR1_DR_L =
0084h, TMR2_DR_L = 0087h, TMR3_DR_L = 008Ah, TMR4_DR_L = 008Dh, or
TMR5_DR_L = 0090h)
Timer Data Register—High Byte
This Read Only register returns the High byte of the current count value of the selected
timer. The Timer Data Register—High Byte, listed in
while the timer is in operation. Reading the current count value does not affect timer oper-
ation.
To read the 16-bit data of the current count value, {TMRx_DR_H[7:0],
TMRx_DR_L[7:0]}, first read the Timer Data Register—Low Byte and then read the
Timer Data Register—High Byte. The Timer Data Register—High Byte value is latched
when a Read of the Timer Data Register—Low Byte occurs.
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
TMRx_DR_L
The Timer Data registers and Timer Reload registers share the same address
space.
The timer data registers and timer reload registers share the same address space.
Value
00h–FFh These bits represent the Low byte of the 2-byte timer data
R
7
0
Description
value, {TMRx_DR_H[7:0], TMRx_DR_L[7:0]}. Bit 7 is bit 7
of the 16-bit timer data value. Bit 0 is bit 0 (lsb) of the 16-bit
timer data value.
R
6
0
R
5
0
R
4
0
Table
Table 34
33, can be read while the timer
R
3
0
Programmable Reload Timers
on page 84, can be read
Product Specification
R
2
0
eZ80F92/eZ80F93
R
1
0
R
0
0
83
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