Z8F1622AR020SG Zilog, Z8F1622AR020SG Datasheet - Page 158
Z8F1622AR020SG
Manufacturer Part Number
Z8F1622AR020SG
Description
IC ENCORE MCU FLASH 16K 64LQFP
Manufacturer
Zilog
Series
Encore!® XP®r
Specifications of Z8F1622AR020SG
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
64-LQFP
Processor Series
Z8F162x
Core
eZ8
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
46
Number Of Timers
4
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
On-chip Adc
10 bit, 12 Channel
For Use With
770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
269-4241
Z8F1622AR020SG
Z8F1622AR020SG
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Price
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PS019921-0308
Address Only Transaction with a 7-bit Address
reading the I
next data byte.
In the situation where software determines if a slave with a 7-bit address is responding
without sending or receiving data, a transaction can be done which only consists of an
address phase.
with a 7-bit address will acknowledge. As an example, this transaction can be used after a
‘write’ has been done to a EEPROM to determine when the EEPROM completes its inter-
nal write operation and is once again responding to I
Acknowledge, the transaction can be repeated until the slave does Acknowledge.
Follow the steps below for an address only transaction to a 7-bit addressed slave:
1. Software asserts the IEN bit in the I
2. Software asserts the TXI bit of the I
3. The I
4. Software responds to the TDRE bit by writing a 7-bit slave address plus write bit (=0)
5. Software sets the START and STOP bits of the I
6. The I
7. The I
8. Software polls the STOP bit of the I
9.
to the I
write operation.
bit.
register.
bit when the address only transaction is completed.
ACK bit is = 1. If the slave does not acknowledge, the ACK bit is = 0. The NCKI
interrupt does not occur in the not acknowledge case because the STOP bit was set.
Software checks the ACK bit of the I
Figure 27. 7-Bit Address Only Transaction Format
2
2
2
C interrupt asserts, because the I
C Controller sends the START condition to the I
C Controller loads the I
2
C Data register. As an alternative this could be a read operation instead of a
2
C Data register. Once the I
Figure 27
S
Slave Address
displays this ‘address only’ transaction to determine if a slave
2
C Shift register with the contents of the I
W = 0 A/A
2
2
2
2
C Control register. Hardware deasserts the STOP
C Control register.
2
C data register has been read, the I
C Control register to enable Transmit interrupts.
C Status register. If the slave acknowledged, the
2
C Data register is empty (TDRE = 1)
2
2
C Control register and clears the TXI
C transactions. If the slave does not
P
Z8 Encore! XP
2
C slave.
Product Specification
®
F64XX Series
2
2
C reads the
C Data
I2C Controller
144
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