PIC16C771/JW Microchip Technology, PIC16C771/JW Datasheet - Page 18
![IC MCU EPROM4KX14 A/D PWM 20CDIP](/photos/12/13/121360/150-20-cdip_sml.jpg)
PIC16C771/JW
Manufacturer Part Number
PIC16C771/JW
Description
IC MCU EPROM4KX14 A/D PWM 20CDIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16C770-ISO.pdf
(220 pages)
2.PIC16C770-ISO.pdf
(6 pages)
3.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C771/JW
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
7KB (4K x 14)
Program Memory Type
EPROM, UV
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
20-CDIP (0.300", 7.62mm) Window
For Use With
ISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMINGDVA16XP200 - ADAPTER ICE 20DIP/SOIC/SSOPAC164028 - MODULE SKT PROMATEII 20SOIC/DIP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
Q1066306
- Current page: 18 of 220
- Download datasheet (4Mb)
PIC16C717/770/771
2.2.2.3
The INTCON Register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
REGISTER 2-3:
DS41120B-page 16
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
INTCON REGISTER
INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB<7:0> pins changed state (must be cleared in software)
0 = None of the RB<7:0> pins have changed state
Legend:
R = Readable bit
- n = Value at POR
R/W-0
Note 1: Individual RB pin interrupt-on-change can be enabled/disabled from the
GIE
Interrupt-on-Change PORTB register (IOCB).
R/W-0
PEIE
R/W-0
T0IE
W = Writable bit
’1’ = Bit is set
R/W-0
INTE
(1)
Note:
(1)
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
RBIE
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
R/W-0
T0IF
2002 Microchip Technology Inc.
x = Bit is unknown
R/W-0
INTF
R/W-x
RBIF
bit 0
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