PIC18LF8722-I/PT Microchip Technology, PIC18LF8722-I/PT Datasheet - Page 205
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PIC18LF8722-I/PT
Manufacturer Part Number
PIC18LF8722-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18LF6627-IPT.pdf
(16 pages)
Specifications of PIC18LF8722-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8722-I/PT
Manufacturer:
EPCOS
Quantity:
30 000
Company:
Part Number:
PIC18LF8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- DV164136 PDF datasheet #3
- PIC18LF6627-IPT PDF datasheet #4
- Current page: 205 of 446
- Download datasheet (7Mb)
18.4.9
The following steps should be taken when configuring
the ECCP1 module for PWM operation using Timer2:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Enable PWM outputs after a new PWM cycle
© 2008 Microchip Technology Inc.
Configure the PWM pins, P1A and P1B (and
P1C and P1D, if used), as inputs by setting the
corresponding TRIS bits.
Set the PWM period by loading the PR2 register.
If auto-shutdown is required do the following:
• Disable auto-shutdown (ECCP1AS = 0)
• Configure source (FLT0, Comparator 1 or
• Wait for non-shutdown condition
Configure the ECCP1 module for the desired
PWM mode and configuration by loading the
CCP1CON register with the appropriate values:
• Select one of the available output
• Select the polarities of the PWM output
Set the PWM duty cycle by loading the CCPR1L
register and CCP1CON<5:4> bits.
For
dead-band delay by loading ECCP1DEL<6:0>
with the appropriate value.
If auto-shutdown operation is required, load the
ECCP1AS register:
• Select the auto-shutdown sources using the
• Select the shutdown states of the PWM
• Set the ECCP1ASE bit (ECCP1AS<7>).
• Configure the comparators using the CMCON
• Configure the comparator inputs as analog
If auto-restart operation is required, set the
P1RSEN bit (ECCP1DEL<7>).
Configure and start TMR2:
• Clear the TMR2 interrupt flag bit by clearing
• Set the TMR2 prescale value by loading the
• Enable Timer2 by setting the TMR2ON bit
has started:
• Wait until TMRx overflows (TMRxIF bit is set).
• Enable the ECCP1/P1A, P1B, P1C and/or
• Clear the ECCP1ASE bit (ECCP1AS<7>).
Comparator 2)
configurations and direction with the
P1M<1:0> bits.
signals with the CCP1M<3:0> bits.
ECCP1AS<2:0> bits.
output pins using the PSS1AC<1:0> and
PSS1BD<1:0> bits.
register.
inputs.
the TMR2IF bit (PIR1<1>).
T2CKPS bits (T2CON<1:0>).
(T2CON<2>).
P1D pin outputs by clearing the respective
TRIS bits.
Half-Bridge
SETUP FOR PWM OPERATION
Output
mode,
set
the
18.4.10
In Sleep mode, all clock sources are disabled. Timer2 or
Timer4 will not increment and the state of the module will
not change. If the ECCP1 pin is driving a value, it will
continue to drive that value. When the device wakes up,
it will continue from this state. If Two-Speed Start-ups are
enabled, the initial start-up frequency from INTOSC and
the postscaler may not be stable immediately.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCP1 module without change. In all other
power-managed modes, the selected power-managed
mode clock will clock Timer2 or Timer4. Other
power-managed mode clocks will most likely be
different than the primary clock frequency.
18.4.10.1
If the Fail-Safe Clock Monitor is enabled, a clock failure
will force the device into the power-managed RC_RUN
mode and the OSCFIF bit (PIR2<7>) will be set. The
ECCP1 will then be clocked from the internal oscillator
clock source, which may have a different clock
frequency than the primary clock.
See the previous section for additional details.
18.4.11
Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the CCP registers to their
Reset states.
This forces the Enhanced CCP module to reset to a
state compatible with the standard CCP module.
PIC18F8722 FAMILY
OPERATION IN POWER-MANAGED
MODES
EFFECTS OF A RESET
Operation with Fail-Safe
Clock Monitor
DS39646C-page 203
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