PIC18LF8722-I/PT Microchip Technology, PIC18LF8722-I/PT Datasheet - Page 2
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PIC18LF8722-I/PT
Manufacturer Part Number
PIC18LF8722-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(6 pages)
3.DV164136.pdf
(446 pages)
4.PIC18LF6627-IPT.pdf
(16 pages)
Specifications of PIC18LF8722-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
70
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
70
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183032, DM183022, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3|5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF8722-I/PT
Manufacturer:
EPCOS
Quantity:
30 000
Company:
Part Number:
PIC18LF8722-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F6627/6722/8627/8722
4. Module: MSSP (I
5. Module: Enhanced Universal
DS80343B-page 2
If the module is in I
performs clock stretching, the first clock pulse after
the slave releases the SCL line may be narrower
than the configured clock width. This may result in
the slave missing the first clock in the next
transmission/reception.
Work around
If the module is in I
the slave perform clock stretching. Alternately, the
master can slow down the SCL clock frequency to
a level where the slave can detect the narrowed
clock pulse.
Date Codes that pertain to this issue:
All engineering and production devices.
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN
• The EUSART is re-enabled (RCSTAx <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-T
1.
2.
3.
4.
5.
Date Codes that pertain to this issue:
All engineering and production devices.
(RCSTAx <7>) bit = 0)
Disable the receive interrupts:
• For RCSTA1 – RC1IE bit (PIE1<5>) = 0
• For RCSTA2 – RC2IE bit (PIE3<5>) = 0
Disable the EUSART:
• For RCSTA1 – SPEN bit (RCSTA1<7>) = 0
• For RCSTA2 – SPEN bit (RCSTA2<7>) = 0
Re-enable the EUSART (RCSTAx <7> = 1).
(See step 1.)
Re-enable the receive interrupts:
• For RCSTA1 – RC1IE bit (PIE1<5>) = 1
• For RCSTA2 – RC2IE bit (PIE3<5>) = 1
Execute a NOP instruction.
(This is the second T
(This is the first T
CY
Synchronous Asynchronous
(EUSART)
delay after re-enabling the EUSART.
2
2
C Master mode and the slave
2
C Master mode, do not have
C™ Master)
CY
CY
delay.)
delay.)
6. Module: Timer1
When Timer1 is running on the Timer1 oscillator, if
Sleep mode is executed immediately after loading
Timer 1 with 0xFFFF, the Timer1 interrupt will not
get set on the first overflow from 0xFFFF to
0x0000.
All subsequent overflows, from 0xFFFF to 0x0000,
will work correctly.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
© 2009 Microchip Technology Inc.