ATMEGA1281-16AU Atmel, ATMEGA1281-16AU Datasheet - Page 157
ATMEGA1281-16AU
Manufacturer Part Number
ATMEGA1281-16AU
Description
IC MCU AVR 128K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA1281-16AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Interface Type
2-Wire/SPI/USART
Total Internal Ram Size
8KB
# I/os (max)
54
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
54
Number Of Timers
6
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZRAVEN, ATAVRRZUSBSTICK, ATAVRISP2, ATAVRRZ201
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
54
Eeprom Memory Size
4KB
Ram Memory Size
8KB
Cpu Speed
16MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRDB101 - MODULE DISPLAY LCD/RGB BACKLIGHT770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2549M–AVR–09/10
Figure 16-12
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn Flag at BOTTOM.
Figure 16-12. Timer/Counter Timing Diagram, no Prescaling
Figure 16-13
Figure 16-13. Timer/Counter Timing Diagram, with Prescaler (f
(PC and PFC PWM)
and ICF n
and ICFn
(CTC and FPWM)
TOVn
(Update at TOP)
(PC and PFC PWM)
TOVn
(CTC and FPWM)
(Update at TOP)
TCNTn
TCNTn
OCRnx
as TOP)
(clk
TCNTn
TCNTn
OCRnx
(clk
as TOP)
clk
clk
clk
clk
I/O
I/O
shows the count sequence close to TOP in various modes. When using phase and
shows the same timing data, but with the prescaler enabled.
(FPWM)
(FPWM)
I/O
Tn
I/O
Tn
/8)
/1)
(if used
(if used
TOP - 1
TOP - 1
TOP - 1
TOP - 1
Old OCRnx Value
ATmega640/1280/1281/2560/2561
Old OCRnx Value
TOP
TOP
TOP
TOP
BOTTOM
BOTTOM
TOP - 1
TOP - 1
clk_I/O
New OCRnx Value
New OCRnx Value
/8)
BOTTOM + 1
BOTTOM + 1
TOP - 2
TOP - 2
157
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