ATXMEGA192A3-MH Atmel, ATXMEGA192A3-MH Datasheet - Page 107

• Manufacturer Part Number: ATXMEGA192A3-MH
• Description: MCU AVR 192K FLASH 1.8V 64-QFN
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA192A3-MH

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 192KB (96K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 16x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATXMEGA192x
• Core: AVR8
• Data Bus Width: 8 bit, 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 50
• Number Of Timers: 8
• Operating Supply Voltage: 1.6 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 2 Channel
• On-chip Dac: 2 bit, 1 Channel
• Package: 64QFN EP
• Device Core: AVR
• Family Name: XMEGA
• Maximum Speed: 32 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ATXMEGA192A3-MU; ATXMEGA192A3-MU

36.1.3
8068T–AVR–12/10
rev. A
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1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
2. ADC gain stage output range is limited to 2.4 V
3. Sampled BOD in Active mode will cause noise when bandgap is used as reference
Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
ADC gain stage output range is limited to 2.4V
Sampled BOD in Active mode will cause noise when bandgap is used as reference
Flash Power Reduction Mode can not be enabled when entering sleep mode
JTAG enable does not override Analog Comparator B output
Bandgap measurement with the ADC is non-functional when V
DAC refresh may be blocked in S/H mode
BOD will be enabled after any reset
Both DFLLs and both oscillators has to be enabled for one to work
Operating frequency and voltage limitations
Inverted I/O enable does not affect Analog Comparator Outpu
simultaneously
If the bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for the another AC, the first comparator will be affected for up
to 1 us and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
Using the BOD in sampled mode when the device is running in Active or Idle mode will add
noise on the bandgap reference for ADC, DAC and Analog Comparator.
Problem fix/Workaround
If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the
BOD must not be set in sampled mode.
–
–
–
–
–
–
–
16x
32x
64x
1x
2x
4x
8x
gain:
gain:
gain:
gain:
gain:
gain:
gain:
300
150
2.4
1.2
0.6
75
38
V
V
V
mV
mV
mV
mV
t
CC
is below 2.7V
XMEGA A3
107