PIC18LF458-I/PT Microchip Technology, PIC18LF458-I/PT Datasheet - Page 51

• Manufacturer Part Number: PIC18LF458-I/PT
• Description: IC MCU CAN FLASH 16K LP 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF458-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 33
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 33
• Interface Type: CAN/I2C/SPI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 4-2:
© 2006 Microchip Technology Inc.
TOSU
TOSH
TOSL
STKPTR
PCLATU
PCLATH
PCL
TBLPTRU
TBLPTRH
TBLPTRL
TABLAT
PRODH
PRODL
INTCON
INTCON2
INTCON3
INDF0
POSTINC0
POSTDEC0
PREINC0
PLUSW0
FSR0H
FSR0L
WREG
INDF1
POSTINC1
POSTDEC1
PREINC1
PLUSW1
FSR1H
FSR1L
BSR
INDF2
POSTINC2
POSTDEC2
PREINC2
PLUSW2
FSR2H
FSR2L
STATUS
TMR0H
TMR0L
T0CON
OSCCON
LVDCON
WDTCON
RCON
Legend:
Note
File Name
1:
2:
3:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
Top-of-Stack High Byte (TOS<15:8>)
Top-of-Stack Low Byte (TOS<7:0>)
Holding Register for PC<15:8>
PC Low Byte (PC<7:0>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
Program Memory Table Latch
Product Register High Byte
Product Register Low Byte
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
Uses contents of FSR0 to address data memory – value of FSR0 offset by W (not a physical register)
Indirect Data Memory Address Pointer 0 Low Byte
Working Register
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
Uses contents of FSR1 to address data memory – value of FSR1 offset by W (not a physical register)
Indirect Data Memory Address Pointer 1 Low Byte
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
Uses contents of FSR2 to address data memory – value of FSR2 offset by W (not a physical register)
Indirect Data Memory Address Pointer 2 Low Byte
Timer0 Register High Byte
Timer0 Register Low Byte
GIE/GIEH
TMR0ON
STKFUL
INT2IP
RBPU
IPEN
Bit 7
—
—
—
—
—
—
—
—
—
—
—
REGISTER FILE SUMMARY
PEIE/GIEL
INTEDG0
STKUNF
T08BIT
INT1IP
Bit 6
—
—
—
—
—
—
—
—
—
—
—
—
INTEDG1
TMR0IE
bit 21
bit 21
IRVST
T0CS
Bit 5
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
Top-of-Stack Upper Byte (TOS<20:16>)
Return Stack Pointer
Holding Register for PC<20:16>
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
LVDEN
INT0IE
INT2IE
T0SE
Bit 4
—
—
—
—
—
—
—
RI
N
Indirect Data Memory Address Pointer 0 High
Indirect Data Memory Address Pointer 1 High
Bank Select Register
Indirect Data Memory Address Pointer 2 High
INT1IE
LVDL3
RBIE
Bit 3
PSA
OV
TO
—
—
—
TMR0IP
TMR0IF
T0PS2
LVDL2
Bit 2
PD
—
—
—
Z
INT0IF
INT2IF
T0PS1
LVDL1
Bit 1
POR
DC
—
—
—
PIC18FXX8
SWDTEN
INT1IF
T0PS0
LVDL0
RBIF
RBIP
Bit 0
SCS
BOR
C
---0 0000
0000 0000
0000 0000
00-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
111- -1-1
11-0 0-00
---- xxxx
xxxx xxxx
xxxx xxxx
---- xxxx
xxxx xxxx
---- 0000
---- xxxx
xxxx xxxx
---x xxxx
0000 0000
xxxx xxxx
1111 1111
---- ---0
--00 0101
---- ---0
0--1 110q 31, 58, 91
POR, BOR
Value on
DS41159E-page 49
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Details on
31, 109
31, 261
31, 272
31, 111
31, 111
Page:
30, 38
30, 38
30, 38
30, 39
30, 40
30, 40
30, 40
30, 68
30, 68
30, 68
30, 68
30, 75
30, 75
30, 79
30, 80
30, 81
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
30, 55
31, 55
31, 55
31, 54
31, 55
31, 55
31, 55
31, 55
31, 55
31, 55
31, 55
31, 57
31, 20