PIC32MX675F256L-80I/PF Microchip Technology, PIC32MX675F256L-80I/PF Datasheet - Page 46
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PIC32MX675F256L-80I/PF
Manufacturer Part Number
PIC32MX675F256L-80I/PF
Description
IC MCU 32BIT 256KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F256L-80I/PF
Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX6xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F256L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC32MX5XX/6XX/7XX
3.2
The PIC32MX5XX/6XX/7XX family core contains sev-
eral logic blocks working together in parallel, providing
an efficient high-performance computing engine. The
following blocks are included with the core:
• Execution Unit
• Multiply/Divide Unit (MDU)
• System Control Coprocessor (CP0)
• Fixed Mapping Translation (FMT)
• Dual Internal Bus interfaces
• Power Management
• MIPS16e Support
• Enhanced JTAG (EJTAG) Controller
3.2.1
The PIC32MX5XX/6XX/7XX family core execution unit
implements a load/store architecture with single-cycle
ALU operations (logical, shift, add, subtract) and an
autonomous multiply/divide unit. The core contains
thirty-two 32-bit General Purpose Registers (GPRs)
used for integer operations and address calculation.
One additional register file shadow set (containing
thirty-two registers) is added to minimize context
switching overhead during interrupt/exception process-
ing. The register file consists of two read ports and one
write port and is fully bypassed to minimize operation
latency in the pipeline.
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
• Logic for branch determination and branch target
• Load aligner
• Bypass multiplexers used to avoid stalls when
• Leading Zero/One detect unit for implementing
• Arithmetic Logic Unit (ALU) for performing bitwise
• Shifter and store aligner
DS61156F-page 46
The execution unit includes:
address
address calculation
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
the CLZ and CLO instructions
logical operations
Architecture Overview
EXECUTION UNIT
3.2.2
The PIC32MX5XX/6XX/7XX family core includes a
Multiply/Divide Unit (MDU) that contains a separate
pipeline for multiply and divide operations. This pipeline
operates in parallel with the Integer Unit (IU) pipeline
and does not stall when the IU pipeline stalls. This
allows MDU operations to be partially masked by
system stalls and/or other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt) oper-
and to determine how many times the operation must
pass through the multiplier. The 16x16 and 32x16 oper-
ations pass through the multiplier once. A 32x32 oper-
ation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit
wide rs, 15 iterations are skipped and for a 24-bit wide
rs, 7 iterations are skipped. Any attempt to issue a sub-
sequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
Table 3-1
until the operation can be reissued) and latency (num-
ber of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
lists the repeat rate (peak issue rate of cycles
MULTIPLY/DIVIDE UNIT (MDU)
© 2010 Microchip Technology Inc.