PIC32MX675F256L-80I/PF Microchip Technology, PIC32MX675F256L-80I/PF Datasheet - Page 2
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PIC32MX675F256L-80I/PF
Manufacturer Part Number
PIC32MX675F256L-80I/PF
Description
IC MCU 32BIT 256KB FLASH 100TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.PIC32MX320F032H-40IPT.pdf
(66 pages)
2.PIC32MX575F256H-80IMR.pdf
(2 pages)
3.PIC32MX575F256H-80IMR.pdf
(254 pages)
4.PIC32MX575F256H-80IMR.pdf
(14 pages)
5.PIC32MX575F256H-80IPT.pdf
(240 pages)
Specifications of PIC32MX675F256L-80I/PF
Core Size
32-Bit
Program Memory Size
256KB (256K x 8)
Core Processor
MIPS32® M4K™
Speed
80MHz
Connectivity
Ethernet, I²C, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP
Controller Family/series
PIC32
Ram Memory Size
64KB
Cpu Speed
80MHz
No. Of Timers
5
Interface
I2C, SPI, UART, USB
No. Of Pwm Channels
5
Embedded Interface Type
I2C, SPI, UART, USB
Rohs Compliant
Yes
Processor Series
PIC32MX6xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX675F256L-80I/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
Additional Notes:
1. extern unsigned int EthPhyMIIMAddress(void):
2. extern unsigned int EthPhyMIIMClock(void):
3. extern eEthRes EthPhyConfigureMII(eEthPhyCfgFlags cFlags):
4. extern eEthRes EthPhyConfigureMdix(eEthOpenFlags oFlags):
1. All functions in the PHY library are defined as weak. You can
2. Take a look in the “..install path\Microchip
3. All functions needed to access the PHY MIIM registers are part of
replace any of the functions with your own implementation if need
arises. The function header in the “..install
path\Microchip\Include\TCPIP-BSD\eth_phy.h” explains what
input/output and behavior the respective function should have.
Solutions\Microchip\TCPIP-BSD\eth_phy\nat_dp83848c.c” or
“..install path\Microchip Solutions\Microchip\TCPIP-
BSD\eth_phy\smsc_8700.c” for an implementation example. Follow
the same approach.
the provided Ethernet library.
a. does not take parameters;
b. Should return the address the PHY responds to. Depends on
c. Can be inlined/#defined
a. does not take parameters;
b. Should return the maximum clock frequency that the PHY can
c. Can be inlined/#defined
a. This function should configure the PHY in one of MII/RMII
b. The relevant input flags are:
c. It should return:
a. The function should configure the MDIX mode for the PHY.
b. The relevant input flags are:
c. It should return:
the hardware design.
use for the MIIM transactions.
operation modes.
ii. National DP83848C supports 25 MHz, for example.
ii. ETH_PHY_CFG_MII if MII configuration is requested
ii. An error code if the requested configuration is not
ii. else ETH_OPEN_MDIX_NORM/ETH_OPEN_MDIX_SWAP for
ii. An error code if the requested mode is not supported.
i. Most PHY’s should support 2 MHz.
i. ETH_PHY_CFG_RMII if RMII configuration is requested
i. ETH_RES_OK for success
i. ETH_OPEN_MDIX_AUTO if auto MDIX is requested
i. ETH_RES_OK for success
Note: all PHY’s respond to address 0.
supported.
normal/swap mode.