PIC16C74A-20/P Microchip Technology, PIC16C74A-20/P Datasheet - Page 112
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PIC16C74A-20/P
Manufacturer Part Number
PIC16C74A-20/P
Description
IC MCU OTP 4KX14 A/D PWM 40DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC16C63A-04SP.pdf
(184 pages)
4.PIC16C72-04SO.pdf
(289 pages)
5.PIC16LC74A-04P.pdf
(8 pages)
Specifications of PIC16C74A-20/P
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Core Processor
PIC
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Number Of I /o
33
Program Memory Type
OTP
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 8x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
192Byte
Cpu Speed
20MHz
No. Of Timers
3
Package
40PDIP
Device Core
PIC
Family Name
PIC16
Maximum Speed
20 MHz
Operating Supply Voltage
5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
33
Interface Type
I2C/SPI/USART
On-chip Adc
8-chx8-bit
Number Of Timers
3
Core
PIC
Processor Series
PIC16C
Maximum Clock Frequency
20 MHz
Data Ram Size
192 B
Data Rom Size
192 B
Mounting Style
Through Hole
A/d Bit Size
8 bit
A/d Channels Available
8
Height
3.81 mm
Length
52.26 mm
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Supply Voltage (max)
6 V
Supply Voltage (min)
4 V
Width
13.84 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
444-1001 - DEMO BOARD FOR PICMICRO MCU
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C74A-20/PQ
Manufacturer:
Microchip Technology
Quantity:
10 000
Company:
Part Number:
PIC16C74A-20/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16C7X
12.3.2
Once Synchronous mode is selected, reception is
enabled
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, then only a single
word is received. If enable bit CREN is set, the recep-
tion is continuous until CREN is cleared. If both bits are
set then CREN takes precedence. After clocking the
last bit, the received data in the Receive Shift Register
(RSR) is transferred to the RCREG register (if it is
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is
reset by the hardware. In this case it is reset when the
RCREG register has been read and is empty. The
RCREG is a double buffered register, i.e. it is a two
deep FIFO. It is possible for two bytes of data to be
received and transferred to the RCREG FIFO and a
third byte to begin shifting into the RSR register. On the
clocking of the last bit of the third byte, if the RCREG
register is still full then overrun error bit OERR
(RCSTA<1>) is set. The word in the RSR will be lost.
The RCREG register can be read twice to retrieve the
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set,
transfers from the RSR to the RCREG are inhibited, so
it is essential to clear bit OERR if it is set. The 9th
receive bit is buffered the same way as the receive
data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
read the RCSTA register before reading RCREG in
order not to lose the old RX9D information.
TABLE 12-9:
DS30390E-page 112
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear.
USART SYNCHRONOUS MASTER
RECEPTION
by
Name
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG
setting
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Baud Rate Generator Register
PSPIE
PSPIF
CSRC
SPEN
Bit 7
either
(1)
(1)
ADIF
ADIE
Bit 6
RX9
TX9
enable
SREN
TXEN
RCIE
RCIF
Bit 5
bit
CREN
SYNC
TXIE
Bit 4
TXIF
SREN
SSPIE CCP1IE
SSPIF
Bit 3
—
—
CCP1IF
BRGH
FERR
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
Bit 2
Initialize the SPBRG register for the appropriate
baud rate. (Section 12.1)
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
TMR2IF
TMR2IE
OERR
TRMT
Bit 1
TMR1IF
TMR1IE
RX9D
TX9D
Bit 0
1997 Microchip Technology Inc.
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
other Resets
Value on all
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000