AT91SAM7L64-CU Atmel, AT91SAM7L64-CU Datasheet - Page 194
![MCU ARM7 64K HS FLASH 144-LFBGA](/photos/12/13/121356/144-lfbga_sml.jpg)
AT91SAM7L64-CU
Manufacturer Part Number
AT91SAM7L64-CU
Description
MCU ARM7 64K HS FLASH 144-LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7L64-CU.pdf
(564 pages)
Specifications of AT91SAM7L64-CU
Core Processor
ARM7
Core Size
16/32-Bit
Speed
36MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.55 V ~ 1.8 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LFBGA
Processor Series
AT91SAMx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
6 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
36 MHz
Number Of Programmable I/os
80
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM7L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
For Use With
AT91SAM7L-STK - KIT EVAL FOR AT91SAM7LAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
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Part Number
Manufacturer
Quantity
Price
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23.7.2
23.7.2.1
23.7.2.2
194
AT91SAM7L128/64 Preliminary
Interrupt Latencies
External Interrupt Edge Triggered Source
External Interrupt Level Sensitive Source
Global interrupt latencies depend on several parameters, including:
This section addresses only the hardware resynchronizations. It gives details of the latency
times between the event on an external interrupt leading in a valid interrupt (edge or level) or the
assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the pro-
cessor. The resynchronization time depends on the programming of the interrupt source and on
its type (internal or external). For the standard interrupt, resynchronization times are given
assuming there is no higher priority in progress.
The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt
sources.
Figure 23-6.
Figure 23-7.
• The time the software masks the interrupts.
• Occurrence, either at the processor level or at the AIC level.
• The execution time of the instruction in progress when the interrupt occurs.
• The treatment of higher priority interrupts and the resynchronization of the hardware signals.
External Interrupt Edge Triggered Source
External Interrupt Level Sensitive Source
(Negative Edge)
(Positive Edge)
IRQ or FIQ
IRQ or FIQ
nIRQ
MCK
nFIQ
(High Level)
(Low Level)
IRQ or FIQ
IRQ or FIQ
nIRQ
nFIQ
MCK
Maximum IRQ Latency = 4 Cycles
Maximum FIQ Latency = 4 Cycles
Latency = 3 Cycles
Latency = 3 cycles
Maximum IRQ
Maximum FIQ
6257A–ATARM–20-Feb-08
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