PIC18F4680-I/ML Microchip Technology, PIC18F4680-I/ML Datasheet - Page 10

• Manufacturer Part Number: PIC18F4680-I/ML
• Description: IC MCU FLASH 32KX16 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4680-I/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3328Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C, SPI, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 44
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 11 bit
• Package: 44QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNI3-DB18F4680 - BOARD DAUGHTER ICEPIC3444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Details

PIC18F2585/2680/4585/4680
33. Module: ECAN™ Technology
EXAMPLE 6:
34. Module: 10-Bit Analog-to-Digital
DS80202G-page 10
If (RXBnOVFL == 1)
Under specific conditions, the TXBxSIDH register
of the pending message for transmission may be
corrupted. The following conditions must exist for
this event to occur:
1. A transmit message must be pending.
2. All of the receive buffers must be full and a
3. A receiver buffer must be made available
When the AD clock source is selected as 2 T
RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select the AD clock source as 4 T
16 T
2 T
Date Codes that pertain to this issue:
All engineering and production devices.
OSC
received message is in the Message Assembly
Buffer (MAB).
(RXBxCON<RXFUL> set to ‘0’) when a Start-
of-Frame (SOF) is recognized on the CAN bus,
or on the instruction cycle prior to the SOF for
the TXBxSIDH corruption event to occur. The
timing of this event is crucial.
OSC
{
}
Temp_RXREG = RXBx; // Read receive buffer
If (MyFlag)
{
}
or RC.
, 32 T
Converter
If (TXREQ == 1)// Is a transmission pending?
{
}
TXREQ = 1;
MyFlag = 0;
DL
OSC
TXREQ = 0; // Clear transmit request
If (TXABT == 1)// Store transmission aborted status value
(Differential Linearity Error) may
or 64 T
MyFlag = 1;
// Has an overflow occurred?
OSC
// Was previous transmission aborted?
// Set transmit request
// Reset stored transmission aborted status
IL
and avoid selecting
(Integral Linearity
OSC
, 8 T
OSC
OSC
or
,
Work around
Ensure that a receive buffer overflow condition
does not occur, and/or ensure that a transmit
request is not pending, if a receive buffer overflow
condition does exist.
The pseudo-code segment in Example 6 is an
example of how to disable a pending transmission.
This code is for illustration purposes only.
Date Codes that pertain to this issue:
All engineering and production devices.
© 2007 Microchip Technology Inc.