PIC32MX460F512L-80I/PT Microchip Technology, PIC32MX460F512L-80I/PT Datasheet - Page 7
![IC PIC MCU FLASH 512K 100-TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
PIC32MX460F512L-80I/PT
Manufacturer Part Number
PIC32MX460F512L-80I/PT
Description
IC PIC MCU FLASH 512K 100-TQFP
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
6.PIC32MX460F256L-80IPT.pdf
(632 pages)
7.PIC32MX320F064H-40IMR.pdf
(172 pages)
Specifications of PIC32MX460F512L-80I/PT
Program Memory Type
FLASH
Program Memory Size
512KB (512K x 8)
Package / Case
100-TFQFP
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
85
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
I2C , SPI , UART
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
85
Number Of Timers
5 x 16 bit, 1 x 32 bit
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320003, DM320002, MA320002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Controller Family/series
PIC32
No. Of I/o's
85
Ram Memory Size
32KB
Cpu Speed
80MHz
No. Of Timers
6
Embedded Interface Type
EUART, I2C, PSP, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKDM320003 - BOARD DEMO USB PIC32 OTGAC244006 - KIT MPLAB REAL ICE TRACEAC164333 - MODULE SKT FOR PM3 100QFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX460F512L-80I/PT
Manufacturer:
VISHAY
Quantity:
3 200
Company:
Part Number:
PIC32MX460F512L-80I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
7. Module: Oscillator
8. Module: DMA
© 2010 Microchip Technology Inc.
After a clock failure event, any write to the
OSCCON register erroneously clears the fail-safe
condition and attempts to switch to a new clock
source that is specified by the NOSC bits in the
OSCCON register.
Work around
After a clock failure event, perform the following
steps:
1. Write ‘000’ to the NOSC bits in the OSCCON
2. Modify the OSCCON register with any value
Affected Silicon Revisions
In Pattern Match mode, the DMA will generate up
to three additional byte writes to the destination
address, after the Pattern Detection event has
occurred, when performing transfers with the
DCHxSSIZ set to greater than 1.
Work arounds
Work around 1:
The destination buffer needs to be large enough to
accommodate the extra bytes (up to 3 extra bytes).
Work around 2:
Set the destination size register to 1.
Work around 3:
Set the source size register to 1.
Affected Silicon Revisions
B2
B2
X
X
register to select the Fast RC oscillator. This
will ensure that an erroneous clock switch
selects the known good on-chip Fast RC
oscillator.
your application requires.
B3
B3
X
X
B4
B4
X
X
B6
B6
X
X
9. Module: Output Compare
10. Module: PMP
The Output Compare module in PWM mode
outputs a high of period register (PRx) length when
attempting to use PWM values of 0x00 followed by
0x01.
Work around
Do not use a PWM value of 0x01.
Affected Silicon Revisions
In PMP Slave 4B Buffer mode, if the underflow
Status bit OBF (PMSTAT<6>) is cleared at the
same time a PMP read is attempted, the PMP
could receive incorrect data.
Work around
The CPU can read the underflow flag OBUF and
set/clear an I/O pin for the external master device
to read. The state of the pin should indicate to the
external master device that an underflow has
occurred and no additional reads should occur
until the underflow status has been cleared by the
CPU.
Affected Silicon Revisions
B2
B2
X
X
PIC32MX3XX/4XX
B3
B3
X
X
B4
B4
X
X
B6
B6
X
X
DS80440D-page 7