AT89C51CC03C-7CTIM Atmel, AT89C51CC03C-7CTIM Datasheet - Page 82
AT89C51CC03C-7CTIM
Manufacturer Part Number
AT89C51CC03C-7CTIM
Description
IC 8051 MCU FLASH 64K 64BGA
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.AT89C51CC03C-S3RIM.pdf
(198 pages)
2.AT89C51CC03C-S3RIM.pdf
(32 pages)
3.AT89C51CC03C-S3RIM.pdf
(27 pages)
4.AT89C51CC03C-S3RIM.pdf
(184 pages)
Specifications of AT89C51CC03C-7CTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
AT89C51CC03C7CTIM
Available stocks
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Part Number
Manufacturer
Quantity
Price
- AT89C51CC03C-S3RIM PDF datasheet
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Watchdog Timer
Figure 42. Watchdog Timer
82
AT89C51CC03
Fwd Clock
RESET
-
AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT)
that automatically resets the chip if it software fails to reset the WDT before the selected
time interval has elapsed. It permits large Time-Out ranking from 16ms to 2s @Fosc =
12MHz in X1 mode.
This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a Watchdog
Timer reset register (WDTRST) and a Watchdog Timer programming (WDTPRG) regis-
ter. When exiting reset, the WDT is -by default- disable.
To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST
register no instruction in between. When the Watchdog Timer is enabled, it will incre-
ment every machine cycle while the oscillator is running and there is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 96xT
should be serviced in those sections of code that will periodically be executed within the
time required to prevent a WDT reset
Note:
-
WDTPRG
-
CLOCK
When the Watchdog is enable it is impossible to change its period.
WDTRST
Fwd
-
14-bit COUNTER
Enable
-
2
OSC
1
, where T
÷ PS
0
WR
OSC
÷ 6
=1/F
Control
Decoder
OSC
7-bit COUNTER
. To make the best use of the WDT, it
Outputs
CPU and Peripheral
Clock
4182E–CAN–05/04
RESET
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